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| 型號(hào)： | AM49DL3208GB70FS |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA69 |
| 封裝： | 8 X 10 MM, FBGA-69 |
| 文件頁數(shù)： | 51/61頁 |
| 文件大小： | 904K |
| 代理商： | AM49DL3208GB70FS |
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March 12, 2004
Am49DL3208G
53
ADV ANCE
I N FO RMAT I O N
PSEUDO SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
CW is measured from CE1#s going low to the end of write.
3. t
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. t
AS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP is measured from the beginning of write
to the end of write.
Figure 30.
Pseudo SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
55
70
t
WC
Write Cycle Time
Min
55
70
ns
t
Cw
Chip Enable to End of Write
Min
45
55
ns
t
AS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
45
55
ns
t
BW
UB#s, LB#s to End of Write
Min
45
55
ns
t
WP
Write Pulse Time
Min
45
55
ns
t
WR
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Min
0
ns
Max
25
t
DW
Data to Write Time Overlap
Min
40
ns
t
DH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
Min
5
ns
Address
CE1#s
Data Undefined
WE#
Data In
Data Out
tWC
tCW
(See Note 1)
tAW
High-Z
Data Valid
CE2s
tCW
(See Note 1)
tWP
(See Note 4)
tAS
(See Note 3)
tWR
tDW
tDH
tOW
tWHZ
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