參數(shù)資料
型號： AM49DL3208GB70FS
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA69
封裝： 8 X 10 MM, FBGA-69
文件頁數(shù)： 49/61頁
文件大小： 904K
代理商： AM49DL3208GB70FS
March 12, 2004
Am49DL3208G
51
ADV ANCE
I N FO RMAT I O N
PSEUDO SRAM AC CHARACTERISTICS
Power Up Time
When powering up the SRAM, maintain V
CCs for 100 s minimum with CE#1s at VIH.
Read Cycle
Notes:
1. CE1#s = OE# = V
IL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
2. Do not access device with cycle timing shorter than t
RC for continuous periods < 10 s.
Figure 28.
Pseudo SRAM Read Cycle—Address Controlled
Parameter
Symbol
Description
Speed
Unit
55
70
t
RC
Read Cycle Time
Min
55
70
ns
t
AA
Address Access Time
Max
55
70
ns
t
CO1, tCO2
Chip Enable to Output
Max
55
70
ns
t
OE
Output Enable Access Time
Max
30
35
ns
t
BA
LB#s, UB#s to Access Time
Max
55
70
ns
t
LZ1, tLZ2
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
Min
5
ns
t
BLZ
UB#, LB# Enable to Low-Z Output
Min
5
ns
t
OLZ
Output Enable to Low-Z Output
Min
5
ns
t
HZ1, tHZ2
Chip Disable to High-Z Output
Max
20
25
ns
t
BHZ
UB#s, LB#s Disable to High-Z Output
Max
20
25
ns
t
OHZ
Output Disable to High-Z Output
Max
20
25
ns
t
OH
Output Data Hold from Address Change
Min
10
ns
Address
Data Out
Previous Data Valid
Data Valid
tAA
tRC
tOH
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