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| 型號： | AM45DL6408G |
| 英文描述： | 250NS, CERDIP, 883C; LEV B COMPLIANT(EEPROM) |
| 中文描述： | 64兆位（8米× 8位/ 4米× 16位）CMOS和8兆位（1 M中的x 8-Bit/512畝x 16位）（初步） |
| 文件頁數(shù)： | 2/64頁 |
| 文件大小： | 1191K |
| 代理商： | AM45DL6408G |
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PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication#
26502
Issue Date:
August 28, 2002
Rev:
A
Amendment/
+3
Am45DL32x8G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash
Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) CompactCell
TM
Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
Power supply voltage of 2.7 to 3.3 volt
I
I
High performance
— Access time as fast as 70 ns
Package
— 73-Ball FBGA
Operating Temperature
— –40°C to +85°C
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Flash Memory Features
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in the other bank.
— Zero latency between read and write operations
I
Manufactured on 0.17 μm process technology
SecSi (Secured Silicon) Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
—
Customer lockable:
Sector is one-time programmable. Once
sector is locked, data cannot be changed.
I
Zero Power Operation
—
Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
I
Top or bottom boot sectors
Compatible with JEDEC standards
—
Pinout and software compatible with single-power-supply
flash standard
I
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PERFORMANCE CHARACTERISTICS
High performance
—
Access time as fast as 70 ns
—
Program time: 4 μs/word typical utilizing Accelerate function
I
Ultra low power consumption (typical values)
—
2 mA active read current at 1 MHz
—
10 mA active read current at 5 MHz
—
200 nA in standby or automatic sleep mode
I
Minimum 1 million erase cycles guaranteed per sector
20 year data retention at 125
°
C
—
Reliable operation for the life of the system
I
I
SOFTWARE FEATURES
Data Management Software (DMS)
—
AMD-supplied software manages data programming,
enabling EEPROM emulation
—
Eases historical sector erase flash limitations
I
Supports Common Flash Memory Interface (CFI)
I
I
Program/Erase Suspend/Erase Resume
—
Suspends program/erase operations to allow
programming/erasing in same bank
Data# Polling and Toggle Bits
—
Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
—
Reduces overall programming time when issuing multiple
program command sequences
I
I
HARDWARE FEATURES
Any combination of sectors can be erased
I
I
Ready/Busy# output (RY/BY#)
—
Hardware method for detecting program or erase cycle
completion
Hardware reset pin (RESET#)
—
Hardware method of resetting the internal state machine to
the read mode
WP#/ACC input pin
—
Write protect (WP#) function protects sectors 0 and 1, or 69
and 70, regardless of sector protect status
—
Acceleration (ACC) function accelerates program timing
Sector protection
—
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
—
Temporary Sector Unprotect allows changing data in
protected sectors in-system
I
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CompactCell SRAM Features
Power dissipation
—
Operating: 30 mA maximum
—
Standby: 100 μA maximum
I
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 2.7 to 3.3 volt
Byte data control: LB#s (DQ7
–
DQ0), UB#s (DQ15
–
DQ8)
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