參數(shù)資料
型號(hào)： AM41DL6408H8H71IS
廠商： Advanced Micro Devices, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVP00; No. of Contacts:6; Connector Shell Size:11; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight
中文描述： 堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁(yè)數(shù)： 15/66頁(yè)
文件大?。?/td> 1123K
代理商： AM41DL6408H8H71IS
November 24, 2003
Am41DL6408H
13
A D V A N C E I N F O R M A T I O N
Table 4.
Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; SRAM Byte Mode, CIOs = V
SS
Legend:
L = Logic Low = V
, H = Logic High = V
, V
= 11.5–12.5
V, V
= 9.0 ± 0.5 V X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, A
IN
= Address In (for Flash Byte Mode, DQ15 = A-1), D
IN
= Data In, D
OUT
=
Data Out, DNU = Do Not Use
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = V
IL
, CE1#s = V
IL
and CE2s = V
IH
at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
IL
, the boot sectors will be protected. If WP#/ACC = V
IH
the boot sectors protection will be removed.
If WP#/ACC = V
ACC
(9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection”.
6. If WP#/ACC = V
IL
, the two outermost boot sectors remain protected. If WP#/ACC = V
IH
, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/ACC = V
HH,
all sectors will be unprotected.
Word/Byte Configuration
The CIOf pin controls whether the device data I/O pins
operate in the byte or word configuration. If the CIOf
pin is set at logic ‘1’, the device is in word configura-
tion, DQ15–DQ0 are active and controlled by CE#f
and OE#.
If the CIOf pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
active and controlled by CE#f and OE#. The data I/O
pins DQ14–DQ8 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE#f and OE# pins to V
IL
. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
. The CIOf pin determines
whether the device outputs array data in words or
bytes.
Operation
(Notes 1, 2)
CE#f CE1#s CE2s OE#
WE#
SA
Addr.
LB#s
(Note 3)
UB#s
(Note 3)RESET#WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
Read from Flash
L
H
X
L
H
X
A
IN
X
X
H
L/H
D
OUT
High-Z
X
L
Write to Flash
L
H
X
H
L
X
A
IN
X
X
H
(Note 3)
D
IN
High-Z
X
L
Standby
V
CC
±
0.3 V
H
X
X
X
X
X
X
X
V
CC
±
0.3 V
H
High-Z
High-Z
X
L
Output Disable
H
L
H
H
H
SA
X
DNU
DNU
H
L/H
High-Z
High-Z
Flash Hardware
Reset
X
H
X
X
X
X
X
X
X
L
L/H
High-Z
High-Z
X
L
Sector Protect
(Note 5)
L
H
X
H
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
X
X
V
ID
L/H
D
IN
X
X
L
Sector Unprotect
(Note 5)
L
H
X
H
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
X
X
V
ID
(Note 6)
D
IN
X
X
L
Temporary
Sector Unprotect
X
H
X
X
X
X
A
IN
X
X
V
ID
(Note 6)
D
IN
High-Z
X
L
Read from SRAM
H
L
H
L
H
SA
A
IN
A
IN
X
X
H
X
D
OUT
D
IN
High-Z
Write to SRAM
H
L
H
X
L
SA
X
X
H
X
High-Z
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AM41DL6408H8H71IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM41DL6408H8H85IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM41LV3204M 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
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