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參數(shù)資料
| 型號(hào)： | Am29PDL128G70R |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control |
| 中文描述： | 128兆位（8米× 16位/ 4米× 32位），3.0伏的CMOS只，同步讀/寫閃存與VersatileIO控制記憶 |
| 文件頁數(shù)： | 53/69頁 |
| 文件大?。?/td> | 1181K |
| 代理商： | AM29PDL128G70R |
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52
Am29PDL128G
July 29, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 9 and
Table 19
for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V
CC
/2. The time from OE# high to
the data bus driven to V
CC
/2 is taken as t
DF
.
.
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
70R, 70
80
90
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
70
80
90
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
70
80
90
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
70
80
90
ns
t
PACC
Page Access Time
Max
25
30
35
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
25
30
35
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Notes 1, 3)
Max
25
30
30
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 3)
Max
25
30
30
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
5
5
5
ns
t
OEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
OH
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
ACC
t
RC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Figure 11.
Read Operation Timings
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