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參數(shù)資料
| 型號： | Am29PDL128G70 |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control |
| 中文描述： | 128兆位（8米× 16位/ 4米× 32位），3.0伏的CMOS只，同步讀/寫閃存與VersatileIO控制記憶 |
| 文件頁數(shù)： | 43/69頁 |
| 文件大?。?/td> | 1181K |
| 代理商： | AM29PDL128G70 |
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42
Am29PDL128G
July 29, 2002
P R E L I M I N A R Y
Legend:
DYB = Dynamic Protection Bit
SSA = SecSi Sector Address (A6:A0) is (0011010).
PD[1:0] = Program Data. Password written in 2 portions.
PPB = Persistent Protection Bit
PWA = Password Address. A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A5:A0) is (001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock bit status.
SA = Sector Address where security command applies. Address bits
A21:A11 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)
WP = PPB Address (A6:A0) is (0111010) (Note 17)
EP = PPB Erase Address (A6:A0) is (1111010)
X = Don
’
t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
1.
2.
3.
See
Table 1
for description of bus operations.
All values are in hexadecimal.
Shaded cells in table denote read cycles. All other cycles are
write operations.
During unlock and command cycles, when lower address bits are
555 or 2AAh as shown in table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don
’
t cares.
Reset command returns device to reading array.
Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate
bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle
6, entire command sequence must be issued and verified again.
Data is latched on rising edge of WE#.
Entire command sequence must be executed for each portion of
password.
4.
5.
6.
7.
8.
9.
10. Password is written over four consecutive cycles at addresses
0-3.
11. A 2 μs timeout is required between any two portions of password.
12. A 100 μs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, entire command
sequence must be issued and verified again. Before issuing
erase command, all PPBs should be programmed to prevent
PPBs overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
16. For all other parts that use the Persistant Protection Bit (axcluding
PDL640G), the WP address is 000010.
Command sequence returns FFh if PPMLB is set.
Table 15.
Sector Protection Command Definitions (x32 Mode)
Command (Notes)
C
1
3
4
6
4
4
4
6
6
3
4
4
4
4
6
4
6
4
Bus Cycles (Notes 1-4)
Addr Data Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Reset
SecSi Sector Entry
SecSi Sector Exit
SecSi Protection Bit Program (5, 6)
Password Program (5, 7, 8)
Password Verify (8, 9)
Password Unlock (7, 10, 11)
PPB Program (6, 12)
All PPB Erase (13, 14)
PPB Lock Bit Set
PPB Lock Bit Status (15)
DYB Write (7)
DYB Erase (7)
DYB or PPB Status
PPMLB Program (6,12)
PPMLB Status (5)
SPMLB Program (6,12)
SPMLB Status (5)
XXX
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
F0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
(BA)555
(BA)555
(BA)555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
88
90
60
38
C8
28
60
60
78
58
48
48
58
60
60
60
60
XX
SSA
XX[0-1]
PWA[0-1]
PWA[0-1]
(SA)WP
(SA)EP
00
68
SSA
48
XX
RD(0)
PD[0-1]
PWD[0-1]
PWD[0-1]
68
60
(SA)WP
(SA)EP
48
40
(SA)WP RD(0)
(SA)WP RD(0)
SA
SA
SA
SA
PL
PL
SL
SL
RD(1)
X1
X0
RD(0)
68
RD(0)
68
RD(0)
PL
48
XX
RD(0)
SL
48
XX
RD(0)
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