參數(shù)資料
型號： AM29LV2562ML120RPII
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 512 Megabit (16 M x 32-Bit/32 M x 16-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
中文描述： 16M X 32 FLASH 3V PROM, 120 ns, PBGA80
封裝： 18 X 12 MM, FBGA-80
文件頁數(shù)： 4/69頁
文件大?。?/td> 1451K
代理商： AM29LV2562ML120RPII
2
Am29LV2562M
October 9, 2003
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV2562M consists of two 256 Mbit, 3.0 volt
single power supply flash memory devices and is or-
ganized as 16,777,216 doublewords or 33,554,432
words. The device has a 32-bit wide data bus that can
also function as an 16-bit wide data bus by using the
WORD# input. The device can be programmed either
in the host system or in standard EPROM program-
mers.
An access time of 120 ns is available. Note that each
access time has a specific operating voltage range
(V
CC
) as specified in the
Product Selector Guide
and
the
Ordering Information
sections. The device is of-
fered in an 80-ball Fortified BGA package. Each de-
vice has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. In addition to
a V
CC
input, a high-voltage
accelerated program
(
WP#/
ACC)
input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard
.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14
(toggle)
status bits
or monitor the
Ready/Busy#
(RY/BY#)
outputs to determine whether the operation
is complete. To facilitate programming, an
Unlock By-
pass
mode reduces command sequence overhead by
requiring only two write cycles to program data instead
of four.
The
VersatileI/O
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
RELATED DOCUMENTS
For a comprehensive information on MirrorBit prod-
ucts, including migration information, data sheets, ap-
plication notes, and software drivers, please see
→
→
相關PDF資料
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