參數(shù)資料
型號(hào)： AM29F200B-150EE
英文描述： 55V Single N-Channel HEXFET Power MOSFET in a TO-262 package; A IRFZ46ZL with Standard Packaging
中文描述： x8/x16閃存EEPROM
文件頁(yè)數(shù)： 13/39頁(yè)
文件大?。?/td> 728K
代理商： AM29F200B-150EE
Am29F002B/Am29F002NB
13
DQ7 or DQ6. See “Write Operation Status” for informa-
tion on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. On the
Am29F002B only, note that a
hardware reset
during
the sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from a “0” back to a “1”.
Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note:
See the appropriate Command Definitions table for
program command sequence.
Figure 2.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. On the
Am29F002B only, note that a
hardware reset
during
the sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the
sector erase command sequence.
The device does
not
require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 μs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
μs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相關(guān)PDF資料
PDF描述
AM29F200B-150EEB 55V Single N-Channel HEXFET Power MOSFET in a TO-262 package; Similar to IRFZ46ZL with Lead Free Packaging
AM29F200B-150EI 30V Single N-Channel HEXFET Power MOSFET in a I-Pak package; Similar to IRLU3303 with Lead Free Packaging
AM29F200B-150FC 55V Single N-Channel HEXFET Power MOSFET in a TO-262 package; Similar to IRF1405ZL with Lead Free Packaging
AM29F200B-150FE A 20V N-channel HEXFET Power MOSFET with 20 volt gate in the DirectFET MT package rated at 150 amperes optimized with low on resistance for applications such as active OR'ing. Shipped in Tape and Reel only. Part is not available in bulk, TR is implied in ; A IRF6609 with Standard Tape and Reel Quantity of 4800
AM29F200B-150FEB x8/x16 Flash EEPROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM29F200BB-120EC 制造商:Advanced Micro Devices 功能描述:
AM29F200BB-120SI 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 120ns 44-Pin SOIC
AM29F200BB-120SI\T 制造商:Spansion 功能描述:Flash Mem Parallel 5V 2M-Bit 256K x 8/128K x 16 120ns 44-Pin SOIC T/R
AM29F200BB-45SI 制造商:Advanced Micro Devices 功能描述:
AM29F200BB-55EF 功能描述:閃存 2M (256KX8/128KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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