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參數(shù)資料
| 型號： | AM29F016B-120DPC1 |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory-Die Revision 1 |
| 中文描述： | 2M X 8 FLASH 5V PROM, 120 ns, UUC37 |
| 封裝： | DIE-37 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 190K |
| 代理商： | AM29F016B-120DPC1 |
2
Am29F016B Known Good Die
2/17/98
S U P P L E M E N T
GENERAL DESCRIPTION
The Am29F016B in Known Good Die (KGD) form is a
16 Mbit, 5.0 volt-only Flash memory. AMD defines KGD
as standard product in die form, tested for functionality
and speed. AMD KGD products have the same relia-
bility and quality as AMD products in packaged form.
Am29F016B Features
The Am29F016B is a 16 Mbit, 5.0 volt-only Flash
memory organized as 2,097,152 bytes of 8 bits each.
The 2 Mbytes of data are divided into 32 sectors of 64
Kbytes each for flexible erase capability. The 8 bits of
data appear on DQ0–DQ7. The Am29F016B is manu-
factured using AMD’s 0.35 μm process technology.
This device is designed to be programmed in-system
with the standard system 5.0 volt V
CC
supply. A 12.0
volt V
PP
is not required for program or erase
operations. The device can also be programmed in
standard EPROM programmers.
The standard device offers an access time of 120 ns,
allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention, the
device has separate chip enable (CE#), write enable
(WE#), and output enable (OE#) controls.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register
contents serve as input to an internal state machine
that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 volt Flash or EPROM devices.
The device is programmed by executing the program
command sequence. This invokes the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The device is erased by executing
the erase command sequence. This invokes the
Embedded Erase algorithm—an internal algorithm that
automatically preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. A sector is typically
erased and verified within one second. The device is
erased when shipped from the factory.
The hardware sector group protection feature disables
both program and erase operations in any combination
of the eight sector groups of memory. A sector group
consists of four adjacent sectors.
The Erase Suspend feature enables the system to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.
True background erase can thus be achieved.
The device requires only a single 5.0 volt power supply
for both read and write functions. Internally generated
and regulated voltages are provided for the program
and erase operations. A low V
CC
detector automatically
inhibits write operations during power transitions. The
host system can detect whether a program or erase
cycle is complete by using the RY/BY# pin, the DQ7
(Data# Polling) or DQ6 (toggle) status bits. After a
program or erase cycle has been completed, the
device automatically returns to the read mode.
A hardware RESET# pin terminates any operation in
progress. The internal state machine is reset to the
read mode. The RESET# pin may be tied to the system
reset circuitry. Therefore, if a system reset occurs
during either an Embedded Program or Embedded
Erase algorithm, the device is automatically reset to the
read mode. This enables the system’s microprocessor
to read the boot-up firmware from the Flash memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot
electron injection.
ELECTRICAL SPECIFICATIONS
Refer to the Am29F016B data sheet, PID 21444, for full
electrical specifications on the Am29F016B in KGD
form.
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F016B KGD
Speed Option (V
CC
= 5.0 V
±
10%)
-120
Max Access Time, t
ACC
(ns)
120
Max CE# Access, t
CE
(ns)
120
Max OE# Access, t
OE
(ns)
50
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29F016B-120DGI1 | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory-Die Revision 1 |
| AM29F016B-120DPI1 | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory-Die Revision 1 |
| AM29F016B-120DTI1 | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory-Die Revision 1 |
| AM29F016B-120DWI1 | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory-Die Revision 1 |
| AM29F016B-120DWC1 | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory-Die Revision 1 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F016B120EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F016B-120EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F016B90EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F016B-90EC | 制造商:Advanced Micro Devices 功能描述:NOR Flash Parallel 5V 16Mbit 2M x 8bit 90ns 48-Pin TSOP 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel 5V 16M-Bit 2M x 8 90ns 48-Pin TSOP |
| AM29F016B-90SC | 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel 5V 16M-Bit 2M x 8 90ns 44-Pin SOP |
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