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參數(shù)資料
| 型號： | AM29DL162DB90PCI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-64 |
| 文件頁數(shù)： | 2/56頁 |
| 文件大?。?/td> | 1752K |
| 代理商： | AM29DL162DB90PCI |
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10
Am29DL16xD
February 14, 2003
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. T he r egis ter is a l a tch us ed to s t ore th e
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1.
Am29DL16xD Device Bus Operations
Legend: L = Logic Low = V
IL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
A
IN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V
IH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. If WP#/ACC = V
IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
Operation
CE#
OE# WE# RESET# WP#/ACC
Addresses
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read
L
H
L/H
AIN
DOUT
DOUT DQ8–DQ14 = High-Z,
DQ15 = A-1
Write
L
H
L
H
AIN
DIN
Standby
VCC ±
0.3 V
XX
VCC ±
0.3 V
H
X
High-Z High-Z
High-Z
Output Disable
L
H
L/H
X
High-Z High-Z
High-Z
Reset
X
L
L/H
X
High-Z High-Z
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
L/H
SA, A6 = L,
A1 = H, A0 = L
D
IN
XX
Sector Unprotect (Note 2)
L
H
L
VID
SA, A6 = H,
A1 = H, A0 = L
DIN
XX
Temporary Sector Unprotect
X
VID
AIN
DIN
High-Z
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