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    參數(shù)資料
    型號： AM29BDD160GT54DPBE
    廠商： ADVANCED MICRO DEVICES INC
    元件分類： PROM
    英文描述： 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
    中文描述： 512K X 32 FLASH 2.7V PROM, 54 ns, PBGA80
    封裝： 13 X 11 MM, 1 MM PITCH, BGA-80
    文件頁數(shù)： 48/80頁
    文件大小： 3476K
    代理商： AM29BDD160GT54DPBE
    50
    Am29BDD160G
    RD(0) = Read Data DQ0 protection indicator bit. If pro-
    tected, DQ0 = 1, if unprotected, DQ0 = 0.
    RD(1) = Read Data DQ1 protection indicator bit. If pro-
    tected, DQ1 = 1, if unprotected, DQ1 = 0.
    SA = Sector Address where security command applies. Ad-
    dress bits A18:A11 uniquely select any sector.
    SL = Persistent Protection Mode Lock Address (A5–A0) is
    (010X10)
    WP = PPB Address (A5–A0) is (111X10)
    X = Don’t care
    PPMLB = Password Protection Mode Locking Bit
    SPMLB = Persistent Protection Mode Locking Bit
    1. 1. See Table 1 for description of bus operations.
    2. 2.All values are in hexadecimal.
    3. 3.Shaded cells in table denote read cycles. All other
    cycles are writer operations.
    4. During unlock cycles, (lower address bits are AAA or
    555h as shown in the table) address bits higher that A11
    (except where BA is required) and data bits higher than
    DQ7 are dont’s cares.
    5. The reset command returns the device to reading the
    array.
    6. The fourth cycle programs the addressed locking bit. The
    fifth and sixth cycles are used to validate whether the bit
    is fully programmed. If DQ0 (in the sixth cycle) reads 0,
    the program command must be issued and verified
    again.
    7. Data is latched on the rising edge of WE#.
    8. The entire four bus-cycle sequence must be entered for
    each portion of the password. PWA (0-3) represent the
    four addresses over which the password is stored. PWD
    (0-3) represent the four word data that comprise the
    password.
    9. The fourth cycle erases all PPBs. The fifth and sixth
    cycles are used to validate whether the bits are fully
    erased. If DQ0 (in the sixed cycle) reads 1, the erase
    command must be issued and verified again.
    10. Before issuing the erase command, all PPBs should be
    programmed in order to prevent over-erasure of PPBs.
    11. In the fourth cycle, 00h indicates PPB set; 01h indicates:
    PPB not set.
    12. The status of additional PPBs and DYBs may be read
    (following the fourth cycle) without reissuing the entire
    command sequence
    相關PDF資料
    PDF描述
    AM29BDD160GT65AKE 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
    AM29BDD160GT65AKF 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
    AM29BDD160GT65AKI 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
    AM29BDD160GT65AKK 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
    AM29BDD160GT65APBE 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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