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參數(shù)資料
| 型號(hào)： | Alert on LAN ASIC |
| 廠商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系統(tǒng)監(jiān)控指示設(shè)備) |
| 中文描述： | 系統(tǒng)監(jiān)測儀器設(shè)備（系統(tǒng)監(jiān)控指示設(shè)備） |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Datasheet
9
Networking Silicon — Alert on LAN* ASIC
Since a hard G2 transition can happen without software knowledge, it is important to disable
watchdog events during G2. This is done by temporarily disabling the watchdog enable while the
PWR_GOOD signal equals 0b. This disables the Watchdog Timer during G2, and if a hard G2
transition occurs, an EEPROM load will reload the Watchdog Timer and possibly set it to be
enabled. At the point that the PWR_GOOD signal transitions high, the Watchdog Timer becomes
enabled (if configured to be enabled) and starts counting from its initial loaded value, essentially
restarting the boot-up time-out timer.
2.4.6
Software Event
The software event also has unique functionality due to its special purpose. The event status bit is
set when a 1b is written to the Software Status Event bit of the Event Status register. After three
packets have been transmitted successfully, this bit is cleared in the Event Status register. However,
a write of 1b at any time to this bit will cause a new event and cause the ASIC to start transmitting
a new series of event packets with the current software information. Software can detect which
packet is in progress by monitoring the CTL_RTCNT bits of the Control Register.
2.4.7
Polarity Functionality
For the six external events, the Event Polarity register informs the Alert on LAN ASIC whether a
particular event is active high or low. The top two bits of the Event Polarity register enable the
special features available for Events 1 and 4 (described above).
2.4.8
Event Status Mask and SMI Mask
The Event Mask register selects the events that can cause an SOS packet transmission as well as
masking the status bits into the packet payload. The SMI Mask selects the events that will cause an
SMI. Both of these registers are loaded by the EEPROM and configurable through the SMB
interface.
While the EEPROM is being read, no events will be observed by the Alert on LAN ASIC,
regardless of either of the mask settings. After the EEPROM is finished loading, the Alert on LAN
ASIC allows the events to enter into the status register, subsequently causing a packet to be sent or
the SMI output to be asserted depending on the setting of the mask registers.
2.4.9
New Event Packet Transmissions
Every time a new event occurs, the following sequence of events will be performed:
1. Any current packet transmission will be aborted.
2. The Quantum counter will increment.
3. The CTL_RTCNT counter value will be reset to 11b.
4. The Retransmission Timer will be reloaded.
5. Data is latched internal to Alert on LAN ASIC for packet creation:
— High byte of Quantum counter
— Low byte of Quantum counter
— Masked Event Status register
— Control register (since it is latched, all 3 packets will show RTCNT equals 11b)
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