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參數(shù)資料
| 型號： | Alert on LAN ASIC |
| 廠商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系統(tǒng)監(jiān)控指示設(shè)備) |
| 中文描述： | 系統(tǒng)監(jiān)測儀器設(shè)備（系統(tǒng)監(jiān)控指示設(shè)備） |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Alert on LAN* ASIC — Networking Silicon
6
Datasheet
setting the ACPI State Indicator in the Control register equal to 10b, where the value of 10b
indicates that the system is in the G2 power state. This typically occurs when the system is
powered down using the 4-second power switch. Loading the EEPROM at this time guarantees
that the Alert on LAN ASIC is placed in a known state since the sudden power loss occurred
without software knowledge.
The Alert on LAN ASIC reads the first 62 words (124 bytes) of the data in the EEPROM and leaves
the last two words (4 bytes) free for vendor information. To ensure that the EEPROM contains
valid data, the Alert on LAN ASIC uses word 3Dh as a checksum. The checksum is a 16-bit value
that causes the sum of all of the ASIC’s data and checksum (in other words, words 00h through
3Dh) to be equal to BABAh. If the checksum is invalid, the ASIC resets most of its registers to the
reset value to prevent it from entering an unpredictable state due to invalid EEPROM data.
The reset values for the registers are such that all packet transmissions and SMI events are disabled
until the EEPROM is loaded. SMB writes should also be prevented by software during an
EEPROM load. SMB reads are always permitted and should be used to check the EEPROM Read
Complete Indication bit in the EEPROM Access register (
Section 4.14, “Register Ch; EEPROM
Access” on page 23
) to determine when the EEPROM load has completed.
The EEPROM interface is a MicroWire** interface that uses 4 control signals: EEPROM Chip
Select (EECS), EEPROM Serial Clock (EESK), EEPROM Data Input (EEDI) and EEPROM Data
Output (EEDO). More details on the MicroWire interface can be found in a MicroWire EEPROM
datasheet.
A GPIO interface is provided to access the EEPROM from software. This allows each EEPROM
bit to be controlled through the SMB register interface. This is the only method in which the
EEPROM can be programmed.
2.4
Event Interface
2.4.1
New Event Definition and Results
There are two components of the event interface. The first portion is the occurrence of an event. An
event occurrence happens any time an event is caused: an event pin is at the active level, a software
event is set via an SMB write, or the Watchdog Timer expires. If the EEPROM does not load, each
of these events will be set in the Event Status register when they happen.
The second part of the event interface is a
new event
. The term new event refers to any event
occurrence that initiates a new packet to be generated and transmitted, regardless of whether a
packet is currently being transmitted or not. A new event occurs whenever one of the following
happens:
A bit in the Event Status register changes from inactive to active and the Event Mask register
bit is already enabled for this event. This occurs any time an unmasked event becomes active
and the status bit was previously 0b, either because the event did not happened before or
because software cleared it.
The Event Status register is already set for a particular event, and the Event Mask is changed
from inactive to active. Since an event that occurs is stored in the Event Status register, the
event does not have to be currently active in order to produce a new event.
For a Software Event, a new event occurs whenever software writes a 1b to the Software Event
Status bit in the Event Status register.
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