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參數資料
| 型號： | AKD4353VF |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數： | 16/33頁 |
| 文件大?。?/td> | 251K |
| 代理商： | AKD4353VF |
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ASAHI KASEI
[AK4353]
MS0016-E-02
2001/05
- 16 -
LRCK
BICK
(64fs)
SDTI
0
22
1
2
24
31
0
1
31
0
1
23:MSB, 0:LSB
22
1
0
Don’t care
23
Lch Data
Rch Data
23
30
22
2
24
23
30
22
1
0
Don’t care
23
22
23
Fig
ure
4. Mode 4 Timing
LRCK
BICK
(64fs)
SDTI
0
3
1
2
24
31
0
1
31
0
1
23:MSB, 0:LSB
22
1
0
Don’t care
23
Lch Data
Rch Data
23
25
3
2
24
23
25
22
1
0
Don’t care
23
23
Figure 5. Mode 5 Timing
n
Data Transmission Format
Data input via SDTI pin is formatted in digital interface format and output via TX pin. Data transmitted on the TX output
is formatted in blocks as shown in figure 6. Each block consists of 192 frames. A frame of data contains two sub-frames.
A sub-frame consists of 32 bits of information. Each data bit received is coded using a bi-phase mark encoding as a two
binary state symbol. The preambles violate bi-phase encoding so they may be differentiated from data. In bi-phase
encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. For a logic
0, the second state of the symbol is the same as the first state. For a 1, the second state is the opposite of the first. Figure
7 illustrates a sample stream of 8 data bits encoded in 16 symbol states.
Frame 191
Frame 0
Frame 1
Sub-frame
Sub-frame
M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2
Figure 6. Block format
0
1
1
0
0
0
0
1
Figure 7. A biphase-encoded bit stream
The sub-frame is defined in the figure below:
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