ASAHI KASEI
[AK4532]
0178-E-02
12
2004/12
4. Explanation of each sequence
4.1. Reset & Power down
INIT1
INITA
Normal
PD
Normal
INIT2
Normal PD+INIT2
Normal
Inhibit(1)
Inhibit(2)
Inhibit(2
Power Supply
PD pin
PD(register)
RST(register)
Internal State
Write to register
External clock
MCLK,LRCK,SCLK
The clocks may be stopped.
INITA
INIT1:
Initializing all registers. The AK4532 exists in the power down state.
INIT2:
Initializing all registers except PD
, RST registers.
INITA:
Initializing the analog section. Initializing period is 516/fs.
PD:
Power down state. All analog outputs are floating.
In case of RST register = “0”, initializing all registers except PD
, RST registers.
Inhibit(1): Inhibits writing to all registers.
Inhibit(2): Inhibits writing to all registers except for PD , RST registers.
The AK4532 operates with the external clocks(MCLK, LRCK, SCLK) during initializing the
analog section.
Figure 1. Reset & Power Down Sequence
4.2. PD pin operation
“H”: Normal operation
“L”: Initializing mode 1(INIT1 in Figure 1)
Initializing all registers.
Inhibits writing to all registers.
The initialization of the analog section starts at rising edge of PD pin.
SDO pin stays “L” during the initializing periods of 516/fs.
Going into power down state.
4.3. RST register operation
“1”: Normal operation
“0”: Initializing mode 2(INIT2 in Figure 1)
Initializing all registers except PD , RST registers.
Inhibits writing to all registers except PD , RST registers.
RST register goes “1” when PD pin goes “L”.
The analog section is not initialized.
4.4. PD register operation
“1”: Normal operation
“0”: Power down
The contents of all registers are held.
PD resister goes “1” when PD pin goes “L”.
All analog outputs(LOUT, ROUT) go floating.
The initialization of the analog section starts at the rising edge of PD resister.
SDO pin stays “L” during the initializing period of 516/fs.
4.5. SDO output pin operation