參數(shù)資料
型號(hào): AK4112B
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: HIGH FEATURE 96kHz 24BIT DIR
中文描述: 特寫96kHz的24位高迪爾
文件頁(yè)數(shù): 13/30頁(yè)
文件大?。?/td> 334K
代理商: AK4112B
ASAHI KASEI
[AK4112B]
MS0078-E-02
2004/04
- 20 -
Serial Control Interface
The internal registers may be either written or read by the 4-wire P interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C0/1 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values. When the state of
P/S pin is changed, the AK4112B should be reset by PDN= “L”.
CDTI
CCLK
CSN
C1
0
123
4
5
67
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0D0
D1
D2
D3
CDTO
Hi-Z
WRITE
CDTI
C1
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0D0
D1
D2
D3
CDTO
Hi-Z
READ
D4
D5
D6
D7
D0
D1
D2
D3
Hi-Z
C1-C0:
Chip Address (Fixed to “00”)
R/W:
READ/WRITE (0:READ, 1:WRITE)
A4-A0:
Register Address
D7-D0:
Control Data
Figure 10. Control I/F Timing
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