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參數(shù)資料
| 型號： | AK4104ET |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO16 |
| 封裝： | 0.65 MM PITCH, LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 503K |
| 代理商： | AK4104ET |
[AK4104]
■ μP Control Interface
The AK4104 can select 4-wire
μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”).
1.4-wire Serial mode (MODE bit = “0”, default)
The internal registers may be either written or read by the 4-wire
μP interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0; fixed to “11”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. CSN should be set to “H” once after the 16th CCLK. For read operations, the CDTO output goes high
impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the
registers to their default values.
CCLK
CSN
0
1
2
34567
8
9
10
11 12
13
14
15
CDTI
C1
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO
Hi-Z
WRITE
CDTI
C1
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO
Hi-Z
READ
D4
D5
D6
D7
D0
D1
D2
D3
Hi-Z
C1-C0: Chip Address: (Fixed to “11”)
R/W:
READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 17. 4-wire
μP I/F Timing
*When the AK4104 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
MS0642-E-00
2007/07
- 14 -
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