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參數(shù)資料
| 型號(hào)： | AK4104ET |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO16 |
| 封裝： | 0.65 MM PITCH, LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 503K |
| 代理商： | AK4104ET |
[AK4104]
OPERATION OVERVIEW
■ Reset and Initialization
The AK4104 should be reset once by bringing PDN = “L” upon power-up. It takes 8 bit clock cycles for the AK4104 to
initialize after PDN pin goes “H”.
■ MCLK and LRCK Relationship
For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through a
frequency divider) or indirectly (for example, as through a DSP). The phase relationship between MCLK and LRCK
should be kept after power-up. The MCLK frequencies shown in Table 1 are supported. The internal clock frequency is
set depending on the external MCLK frequency automatically.
MCLK
Fs
128fs
16k-192kHz
192fs
16k-192kHz
256fs
8k-128kHz
384fs
8k-96kHz
512fs
8k-48kHz
768fs
8k-48kHz
1024fs
8k-32kHz
1536fs
8k-24kHz
Table 1. MCLK Frequency
MS0642-E-00
2007/07
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