2-48 Revision 16 1.2 V DC Core Voltage Table 2-77 Output Data Register Propagation Dela" />
參數(shù)資料
型號(hào): AGLP060V5-VQG176I
廠商: Microsemi SoC
文件頁數(shù): 94/134頁
文件大小: 0K
描述: IC FPGA IGLOO PLUS 60K 176-VQFN
標(biāo)準(zhǔn)包裝: 60
系列: IGLOO PLUS
邏輯元件/單元數(shù): 1584
RAM 位總計(jì): 18432
輸入/輸出數(shù): 137
門數(shù): 60000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 176-TQFP
供應(yīng)商設(shè)備封裝: 176-VQFP(20x20)
IGLOO PLUS DC and Switching Characteristics
2-48
Revision 16
1.2 V DC Core Voltage
Table 2-77 Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std. Units
tOCLKQ
Clock-to-Q of the Output Data Register
1.03
ns
tOSUD
Data Setup Time for the Output Data Register
0.52
ns
tOHD
Data Hold Time for the Output Data Register
0.00
ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
1.22
ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
1.31
ns
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
0.00
ns
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
0.24
ns
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
0.00
ns
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
0.24
ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.19
ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.19
ns
tOCKMPWH
Clock Minimum Pulse Width High for the Output Data Register
0.31
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the Output Data Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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