參數(shù)資料
型號: AGLP060V2CS289I
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA289
封裝: 14 X 14 MM , 1.2 MM HEIGHT, 0.8 MM PITCH, CSP-289
文件頁數(shù): 77/128頁
文件大小: 4383K
代理商: AGLP060V2CS289I
IGLOO PLUS DC and Switching Characteristics
2- 38
R e v i sio n 1 1
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V
applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Timing Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-64 Minimum and Maximum DC Input and Output Levels
1.2 V
LVCMOS1
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL
2 I
IH
3
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA4
Max.
mA4
A5 A5
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
2
20
26
10
Notes:
1. Applicable to IGLOO nano V2 devices operating at VCCI
≥ VCC.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Figure 2-11 AC Loading
Table 2-65 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
01.2
0.6
5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
Test Point
Enable Path
Datapath
5 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Table 2-66 1.2 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
STD
0.98
8.27
0.19
1.57
2.34
0.67
7.94
6.77
3.00
3.11
ns
Note:
For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-67 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
STD
0.98
3.38
0.19
1.57
2.34
0.67
3.26
2.78
2.99
3.24
ns
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. Software default selection highlighted in gray.
相關(guān)PDF資料
PDF描述
AGLP060V2CS289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
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AGLP060V2CSG289I FPGA, 1584 CLBS, 60000 GATES, PBGA289
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