Revision 17 2-35 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) " />
參數(shù)資料
型號: AGLN030V5-ZQNG48
廠商: Microsemi SoC
文件頁數(shù): 98/150頁
文件大?。?/td> 0K
描述: IC FPGA NANO 1KB 30K 48-QFN
標(biāo)準(zhǔn)包裝: 260
系列: IGLOO nano
邏輯元件/單元數(shù): 768
輸入/輸出數(shù): 34
門數(shù): 30000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -20°C ~ 70°C
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN(6x6)
IGLOO nano Low Power Flash FPGAs
Revision 17
2-35
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-51 Minimum and Maximum DC Input and Output Levels
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL 1 IIH 2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.45 VCCI – 0.45
2
9
11
10
4 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.45 VCCI – 0.45
4
17
22
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-9 AC Loading
Table 2-52 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
01.8
0.9
5
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.
Test Point
Enable Path
Datapath
5 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
5 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
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