Revision 17 3-3 should be treated as a sensitive asynchronous signal. When defining pin placement and board layou" />
參數(shù)資料
型號： AGLN010V2-UCG36I
廠商： Microsemi SoC
文件頁數(shù)： 10/150頁
文件大?。?/td> 0K
描述： IC FPGA NANO 1KB 10K 36-UCSP
標準包裝： 714
系列： IGLOO nano
邏輯元件/單元數(shù)： 260
輸入/輸出數(shù)： 23
門數(shù)： 10000
電源電壓： 1.14 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 36-WFBGA，CSBGA
供應商設備封裝： 36-UCSP（3x3）
IGLOO nano Low Power Flash FPGAs
Revision 17
3-3
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO nano devices. The
Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing migration to
larger or smaller IGLOO nano devices while maintaining the same pin location on the board. Refer to the
"Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO nano FPGA Fabric User’s
Guide for more information on I/O states during Flash*Freeze mode.
JTAG Pins
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a
separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB
design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal
pull-up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a
resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired
state.
Note that to operate at all VJTAG voltages, 500
to 1 k will satisfy the requirements. Refer to Table 3-2
for more information.
Table 3-1 Flash*Freeze Pin Locations for IGLOO nano Devices
Package
Flash*Freeze Pin
CS81/UC81
H2
QN48
14
QN68
18
VQ100
27
UC36
E2
Table 3-2 Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
Tie-Off Resistance 1,2
VJTAG at 3.3 V
200
to 1 k
VJTAG at 2.5 V
200
to 1 k
VJTAG at 1.8 V
500
to 1 k
VJTAG at 1.5 V
500
to 1 k
Notes:
1. The TCK pin can be pulled-up or pulled-down.
2. The TRST pin is pulled-down.
3. Equivalent parallel resistance if more than one device is on the JTAG chain
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