2-92 Revision 13 Table 2-144 IGLOOe CCC/PLL Specification For IGLOOe V2 Devices, 1.2 V DC Core Sup" />
參數(shù)資料
型號： AGLE600V5-FGG484I
廠商： Microsemi SoC
文件頁數(shù)： 9/166頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 600K 484-FBGA
標(biāo)準(zhǔn)包裝： 60
系列： IGLOOe
邏輯元件/單元數(shù)： 13824
RAM 位總計： 110592
輸入/輸出數(shù)： 270
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
IGLOOe DC and Switching Characteristics
2-92
Revision 13
Table 2-144 IGLOOe CCC/PLL Specification
For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
160
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
160
MHz
Serial Clock (SCLK) for Dynamic PLL1
60
MHz
Delay Increments in Programmable Delay Blocks2, 3
5804
ps
Number of Programmable Values in Each Programmable Delay
Block
32
Input Cycle-to-Cycle Jitter (peak magnitude)
0.25
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT5
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
External
FB Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
0.50%
0.75%
0.70%
24 MHz to 100 MHz
1.00%
1.50%
1.20%
100 MHz to 160 MHz
2.50%
3.75%
2.75%
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter6
LockControl = 0
4
ns
LockControl = 1
3
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 12, 3, 7
2.3
20.86
ns
Delay Range in Block: Programmable Delay 2 2, 3, 7
0.863
20.86
ns
Delay Range in Block: Fixed Delay 2, 3
5.7
ns
Notes:
1. Maximum value obtained for a Std. speed grade device in Worst Case Commercial Conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-6 for deratings.
3. TJ = 25°C, VCC = 1.5 V
4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help associated with the core for more information.
5. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider
settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output
divider settings.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
7. For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the "Clock Conditioning Circuits in IGLOO and
ProASIC3 Devices" chapter of the IGLOOe FPGA Fabric User’s Guide.
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