參數(shù)資料
型號： AGLE600V5-FG256C
元件分類： FPGA
英文描述： FPGA, 13824 CLBS, 600000 GATES, PBGA256
封裝： 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256
文件頁數(shù)： 153/156頁
文件大?。?/td> 5023K
代理商： AGLE600V5-FG256C
IGLOOe DC and Switching Characteristics
2- 82
Advance v0.3
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Table 2-125 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
1.07
ns
tDDROSUD1
Data_F Data Setup for Output DDR
0.67
ns
tDDROSUD2
Data_R Data Setup for Output DDR
0.67
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
1.38
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.23
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19
ns
tDDROCKMPWH
Clock Minimum Pulse Width HIGH for the Output DDR
0.31
ns
tDDROCKMPWL
Clock Minimum Pulse Width LOW for the Output DDR
0.28
ns
FDDOMAX
Maximum Frequency for the Output DDR
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-126 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =1.14V
Parameter
Description
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
1.60
ns
tDDROSUD1
Data_F Data Setup for Output DDR
1.09
ns
tDDROSUD2
Data_R Data Setup for Output DDR
1.16
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
1.99
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.24
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19
ns
tDDROCKMPWH
Clock Minimum Pulse Width HIGH for the Output DDR
0.31
ns
tDDROCKMPWL
Clock Minimum Pulse Width LOW for the Output DDR
0.28
ns
FDDOMAX
Maximum Frequency for the Output DDR
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
相關(guān)PDF資料
PDF描述
AGLE600V5-FG484C FPGA, 13824 CLBS, 600000 GATES, PBGA484
AGLE600V5-FGG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V5-FGG484C FPGA, 13824 CLBS, 600000 GATES, PBGA484
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