參數(shù)資料
型號: AGLE600V5-FGG256C
元件分類: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA256
封裝: 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-256
文件頁數(shù): 1/156頁
文件大?。?/td> 5023K
代理商: AGLE600V5-FGG256C
October 2008
I
2008 Actel Corporation
IGLOOe Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
Low-Power Active FPGA Operation
Flash*Freeze
Technology
Enables
Ultra-Low
Power
Consumption while Maintaining FPGA Content
Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-
Power Flash*Freeze Mode
High Capacity
600 k to 3 Million System Gates
108 to 504 kbits of True Dual-Port SRAM
Up to 620 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
In-System Programming (ISP) and Security
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
FlashLock to Secure FPGA Contents
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Pro (Professional) I/O
700 Mbps DDR, LVDS-Capable I/Os
1.2
V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 8 Banks per Chip
Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
I/O Registers on Input, Output, and Enable Paths
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay
Schmitt Trigger Option on Single-Ended Inputs
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the IGLOOe Family
Clock Conditioning Circuit (CCC) and PLL
Six CCC Blocks, Each with an Integrated PLL
Configurable
Phase
Shift,
Multiply/Divide,
Delay
Capabilities, and External Feedback
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
True Dual-Port SRAM (except ×18)
ARM Processor Support in IGLOOe FPGAs
M1 IGLOOe Devices—Cortex-M1 Soft Processor Available
with or without Debug
IGLOOe Product Family
IGLOOe Devices
AGLE600
AGLE3000
ARM-Enabled IGLOOe Devices
M1AGLE3000
System Gates
600 k
3 M
VersaTiles (D-flip-flops)
13,824
75,264
Quiescent Current (typical) in Flash*Freeze Mode (W)
49
137
RAM kbits (1,024 bits)
108
504
4,608-Bit Blocks
24
112
FlashROM Bits
1 k
Secure (AES) ISP
Yes
CCCs with Integrated PLLs
66
VersaNet Globals1
18
I/O Banks
88
Maximum User I/Os
270
620
Package Pins
FBGA
FG256, FG484
FG484, FG896
Notes:
1. Refer to the Cortex-M1 Handbook for more information.
2. Six chip (main) and twelve quadrant global networks are available.
3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology handbook.
v1.2
相關(guān)PDF資料
PDF描述
AGLE600V5-FGG484C FPGA, 13824 CLBS, 600000 GATES, PBGA484
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