Revision 13 2-75 1.2 V DC Core Voltage Table 2-128 Output Enable Register Propagation Delays
參數(shù)資料
型號: AGLE600V2-FGG256
廠商: Microsemi SoC
文件頁數(shù): 155/166頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 600K 256-FBGA
標(biāo)準(zhǔn)包裝: 90
系列: IGLOOe
邏輯元件/單元數(shù): 13824
RAM 位總計: 110592
輸入/輸出數(shù): 165
門數(shù): 600000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
IGLOOe Low Power Flash FPGAs
Revision 13
2-75
1.2 V DC Core Voltage
Table 2-128 Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std. Units
tOECLKQ
Clock-to-Q of the Output Enable Register
1.10
ns
tOESUD
Data Setup Time for the Output Enable Register
1.15
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00
ns
tOESUE
Enable Setup Time for the Output Enable Register
1.22
ns
tOEHE
Enable Hold Time for the Output Enable Register
0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
1.65
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
1.65
ns
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.24
ns
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.24
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.19
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
0.19
ns
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register
0.31
ns
tOECKMPWL
Clock Minimum Pulse Width LOW for the Output Enable Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
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