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參數(shù)資料
| 型號(hào)： | AFS250-2PQG208I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 165/334頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2MB FLASH 250K 208PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Fusion® |
| RAM 位總計(jì)： | 36864 |
| 輸入/輸出數(shù)： | 93 |
| 門數(shù)： | 250000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
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Fusion Family of Mixed Signal FPGAs
Revision 4
2-231
XTAL2
Crystal Oscillator Circuit Input
Input to crystal oscillator circuit. Pin for connecting external crystal, ceramic resonator, RC network, or
external clock input. When using an external crystal or ceramic oscillator, external capacitors are also
recommended (Please refer to the crystal oscillator manufacturer for proper capacitor value).
If using external RC network or clock input, XTAL1 should be used and XTAL2 left unconnected. In the
case where the Crystal Oscillator block is not used, the XTAL1 pin should be connected to GND and the
XTAL2 pin should be left floating.
Security
Fusion devices have a built-in 128-bit AES decryption core. The decryption core facilitates highly secure,
in-system programming of the FPGA core array fabric and the FlashROM. The FlashROM and the FPGA
core fabric can be programmed independently from each other, allowing the FlashROM to be updated
without the need for change to the FPGA core fabric. The AES master key is stored in on-chip nonvolatile
memory (flash). The AES master key can be preloaded into parts in a security-protected programming
environment (such as the Microsemi in-house programming center), and then "blank" parts can be
shipped to an untrusted programming or manufacturing center for final personalization with an AES-
encrypted bitstream. Late stage product changes or personalization can be implemented easily and with
high level security by simply sending a STAPL file with AES-encrypted data. Highly secure remote field
updates over public networks (such as the Internet) are possible by sending and programming a STAPL
file with AES-encrypted data. For more information, refer to the Fusion Security application note.
128-Bit AES Decryption
The 128-bit AES standard (FIPS-197) block cipher is the National Institute of Standards and Technology
(NIST) replacement for DES (Data Encryption Standard FIPS46-2). AES has been designed to protect
sensitive government information well into the 21st century. It replaces the aging DES, which NIST
adopted in 1977 as a Federal Information Processing Standard used by federal agencies to protect
sensitive, unclassified information. The 128-bit AES standard has 3.4 × 1038 possible 128-bit key
variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit AES cipher text
using exhaustive techniques. Keys are stored (protected with security) in Fusion devices in nonvolatile
flash memory. All programming files sent to the device can be authenticated by the part prior to
programming to ensure that bad programming data is not loaded into the part that may possibly damage
it. All programming verification is performed on-chip, ensuring that the contents of Fusion devices remain
as secure as possible.
AES decryption can also be used on the 1,024-bit FlashROM to allow for remote updates of the
FlashROM contents. This allows for easy support of subscription model products and protects them with
measures designed to provide the highest level of security available. See the application note Fusion
Security for more details.
AES for Flash Memory
AES decryption can also be used on the flash memory blocks. This provides the best available security
during update of the flash memory blocks. During runtime, the encrypted data can be clocked in via the
JTAG interface. The data can be passed through the internal AES decryption engine, and the decrypted
data can then be stored in the flash memory block.
Programming
Programming can be performed using various programming tools, such as Silicon Sculptor II (BP Micro
Systems) or FlashPro3 (Microsemi).
The user can generate STP programming files from the Designer software and can use these files to
program a device.
Fusion devices can be programmed in-system. During programming, VCCOSC is needed in order to
power the internal 100 MHz oscillator. This oscillator is used as a source for the 20 MHz oscillator that is
used to drive the charge pump for programming.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A54SX16P-PQ208 | IC FPGA SX 24K GATES 208-PQFP |
| AMM22DTAH | CONN EDGECARD 44POS R/A .156 SLD |
| 8655MHRA3701LF | BACKSHELL DB37 45DEG METAL SHLD |
| AMM22DTAD | CONN EDGECARD 44POS R/A .156 SLD |
| A54SX16P-PQG208 | IC FPGA SX 24K GATES 208-PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFS250-2PQG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| AFS250-2PQG256I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| AFS250-2PQG256PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| AFS250-2QN256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| AFS250-2QN256I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
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