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參數(shù)資料
| 型號(hào)： | AFE2124E |
| 英文描述： | Dual HDSL/SDSL ANALOG FRONT END |
| 中文描述： | 雙HDSL / SDSL是模擬前端 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 187K |
| 代理商： | AFE2124E |
6
AFE2124
THEORY OF OPERATION
The AFE2124 has two HDSL Analog Front End (AFE)
circuits on chip (channel A and channel B). Each AFE is
functionally equivalent to an AFE1124. Each AFE consists
of a transmit and a receive channel which interfaces to a
HDSL DSP through a six-wire serial interface—three wires
for the transmit channel and three wires for the receive
channel. It interfaces to the HDSL telephone line trans-
former and external compromise hybrid through transmit
and receive analog connections.
The transmit channel consists of a switched-capacitor pulse
forming network followed by a differential line driver. The
pulse-forming network receives 2-bit digital symbol data
and generates a filtered 2B1Q analog output waveform. The
differential line driver uses a composite output stage com-
bining class B operation (for high efficiency driving large
signals) with class AB operation (to minimize crossover
distortion).
The receive channel is designed around a fourth-order delta
sigma analog-to-digital converter. It includes a difference
amplifier designed to be used with an external compromise
hybrid for first-order analog echo cancellation. A program-
mable gain amplifier with gains of 0dB to +12dB is also
included. The delta sigma modulator, operating at a 24x
FIGURE 2. Transmit Timing Diagram.
oversampling ratio, produces a 14-bit output at rates up to
584kHz (1.168Mbps).
The receive channel operates by summing the two differen-
tial inputs, one from the line (rxLINE) and the other from the
compromise hybrid (rxHYB). The connection of these two
inputs so that the hybrid signal is subtracted from the line
signal is described in the paragraph titled “Echo Cancella-
tion in the AFE.” The equivalent gain for each input in the
difference amp is one. The resulting signal then passes to a
programmable gain amplifier which can be set for gains of
0dB through +12dB. Following the PGA, the ADC converts
the signal to a 14-bit digital word.
The serial interface consists of three wires for transmit and
three wires for receive. The three-wire transmit interface is
transmit baud rate clock, transmit 48x oversampling clock
and Data Out. The three-wire receive interface is receive
baud rate clock, receive 48x oversampling clock and Data
In. The transmit and receive clocks are supplied to the
AFE2124 from the DSP and are completely independent.
DIGITAL DATA INTERFACE
Data is received by the AFE2124 from the DSP on the Data
In line. Data is transmitted from the AFE2124 to the DSP on
the Data Out line. The following paragraphs describe the
timing of these signals and data structure.
FIGURE 1. DSP Interface.
HDSL
DSP
1/2
AFE2124
rxbaudCLK
rx48xCLK
Data Out
txbaudCLK
tx48xCLK
Data In
Data In
from DSP
tx48xCLK
from DSP
txbaudCLK
from DSP
4ns
MSB
Bit 15
48
1
2
3
4
15
16
47
48
1
LSB
Bit 0
MSB
Bit 15
4ns
4ns
4ns
A
B
Transmit Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the txbaudCLK
can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the txbaudCLK
can occur within 4ns (on either side) of any rising edge of tx48xCLK. (3) The AFE2124 reads Data In on the rising edge
of the tx48xCLK. Data In must be stable at least 4ns before the rising edge of tx48xCLK and it must remain stable at
least 4ns after the rising edge of tx48xCLK. (4) Symbol data is transferred to the transmit pulse former after the LSB is
read. The output analog symbol data reaches the peak of the symbol approximately 24 tx48xCLK periods later.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE2124E/1K | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124E/1KG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2124EG4 | 功能描述:電信線路管理 IC Dual HDSL/SDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE2126 | 制造商:BB 制造商全稱:BB 功能描述:Dual HDSL/SDSL ANALOG FRONT END |
| AFE2126E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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