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參數(shù)資料
| 型號： | AFE1231KG4 |
| 英文描述： | G.SHDSL ANALOG FRONT-END |
| 中文描述： | 灣SHDSL的模擬前端 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 313K |
| 代理商： | AFE1231KG4 |
AFE1230
SBWS015A
8
TABLE IV. tx Data Structure.
TABLE V. tx Data Format.
BIT
DESCRIPTION
BIT STATE
OUTPUT STATE
47-32
31
tx D/A Converter Word 1
Power Control
XXXX
0
1
0
00
01
10
11
0
1
00
01
10
11
0
1
XXXX
00
000
001
010
011
100
101
110
111
00
01
10
11
0
16-Bit Binary Two's Complement Word to tx D/A Converter (MSB First)
Normal Power, Any Speed
Low Power, Low Speed (< 1/2 Full Word Rate)
Reserved for Future Use
0.25x Word Rate
0.38x Word Rate
0.5x Word Rate
Not Used
Fifth-Order Butterworth
Seventh-Order Butterworth
Normal Transient Power
Normal Transient Power
–
6dB
Normal Transient Power
–
12dB
Normal Transient Power
–
18dB
0.25x Word Rate
0.5x Word Rate
16-Bit Binary Two's Complement Word to tx D/A Converter (MSB First)
Reserved for Future Use
rx Gain = 0dB
rx Gain = 3dB
rx Gain = 6dB
rx Gain = 9dB
rx Gain = 12dB
rx Gain = 15dB
rx Gain = 18dB
rx Gain = 21dB
Normal Operation
Loop-Back Mode Digital, tx Data to rx Data
Hybrid Mode, Line Input Connected to V
CM
Line Mode, Hybrid Input Connected to V
CM
Reserved
30
Reserved
(1)
29-28
tx Cutoff Frequency Control
27
tx Filter Order
26-25
tx Power Backoff
24
rx Cutoff Frequency Control
23-8
7-6
5-3
tx D/A Converter Word 2
Reserved
(1)
rx Gain Settings
2-1
Loop-Back Control
0
Reserved
(1)
NOTE: (1) Reserved Bits must be set to 0.
16
MSB
1
1
2
1
1
2
tx Power Backoff
rx Cutoff Frequency
tx Filter Order
tx Cutoff Frequency
Spare
Loopback
Spare
rx Gain
Spare
tx DAC Word 2
Low Power
tx DAC Word 1
16
2
3
2
1
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