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參數(shù)資料
| 型號(hào)： | AFE1205 |
| 英文描述： | LJT 18C 18#20 PIN PLUG |
| 中文描述： | 2Mbps的，單對(duì)HDSL模擬前端 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 196K |
| 代理商： | AFE1205 |
8
AFE1205
TIMING DIAGRAM
FIGURE 3. Timing Diagram.
RECEIVE TIMING
The rxSYNC signal controls portions of the A/D converter’s
decimation filter and the data output timing of the A/D
converter. It is generated at the symbol rate by the user and
must be synchronized with txCLK. The rising edge of
rxSYNC can occur at the falling edge of txCLK or it can be
shifted by the user in increments of 1/48 of a symbol period
to one of 47 discrete delay times after the falling edge of
txCLK.
RECEIVE OUTPUT DATA RATE
The receive channel delta-sigma A/D converter of the
AFE1205 uses a modulator which operates at an oversampling
rate of 24X the symbol rate. The A/D converter’s decimation
filter downsamples the modulator output by a factor of 12.
The bandwidth of the decimation filter is equal to one-half
the symbol rate. This yields two output words per symbol
period. These two output words are shown as Data 1 and
Data 1a in Figure 3. The specifications of the AFE1205
assume that one A/D converter output is used per symbol
period and the other output is ignored. The Receive Timing
diagram above suggests using the rising edge of the rxSYNC
pulse to read the first data output in a symbol period. Either
data output may be used. Both data outputs may be used for
more flexible post-processing.
t
tx1
t
tx2
t
tx1
/4
t
tx1
/2
(n + 29.5) t
tx1
/48
(n + 5.5) t
tx1
/48
Data 1
Data 1a
Data 2
3t
tx1
/4
txCLK
Transmit Timing
txDAT
(+3 Symbol)
txDAT (+1 Symbol)
txDAT (–1 Symbol)
txDAT (–3 Symbol)
rxSYNC
Receive Timing
rxD13 - rxD0
t
tx1
/24 min
nt
tx1
/48
±
t
tx1
/96
5ns
5ns
NOTES: (1) An output symbol must be sent to the AFE1205 through the txDAT pin during each baud period. (2) Any transmit sequence
not shown above will result in a zero symbol. (3) All transitions are specified relative to the falling edge of txCLK. (4) For each new
symbol period, the initial txDAT transition occurs on the falling edge of txCLK. (5) The maximum allowable timing error for the initial
txDAT transition is
±
t
tx1
/10 (
±
86ns for single pair E1 rates). The maximum allowable timing error for the two subsequent txDAT
transitions is
±
t
/12 (
±
72ns for single pair E1 rates). (6) The txDAT input is read by the AFE1205 at 1/8, 3/8, and 5/8 of a symbol
period from the falling edge of txCLK. (7) rxSYNC can shift to one of 48 discrete delay times from the falling edge of txCLK. (8) It is
recommended that rxD13 - rxD0 be read on the rising edge of rxSYNC.
5ns
5ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AFE1205E | Circular Connector; No. of Contacts:18; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-18 RoHS Compliant: No |
| AFE1224 | 2Mbps, Single Pair ANALOG FRONT END |
| AFE1224E | Circular Connector; No. of Contacts:18; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-18 RoHS Compliant: No |
| AFE1230 | G.SHDSL ANALOG FRONT-END |
| AFE1230E | G.SHDSL ANALOG FRONT-END |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1205E | 功能描述:電信線路管理 IC 2Mbps Sngl Pair HDSL Anlg Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1205E/1K | 功能描述:IC HDSL ANALOG FRONT END 48SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AFE1205E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1205EG4 | 功能描述:電信線路管理 IC 2Mbps Sngl Pair HDSL Anlg Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1224 | 制造商:BB 制造商全稱:BB 功能描述:2Mbps, Single Pair ANALOG FRONT END |
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