參數(shù)資料
型號: AFE1104
英文描述: LJT 12C 8#20 4#16 PIN PLUG
中文描述: HDSL / MDSL模擬前端
文件頁數(shù): 2/10頁
文件大?。?/td> 203K
代理商: AFE1104
2
AFE1104
SPECIFICATIONS
Typical at 25
°
C, AV
DD
= +5V, DV
DD
= +3.3V, f
tx
= 584kHz (E1 rate), unless otherwise specified.
AFE1104E
PARAMETER
COMMENTS
MIN
TYP
MAX
UNITS
RECEIVE CHANNEL
Number of Inputs
Input Voltage Range
Common-Mode Voltage
Input Impedance
Input Capacitance
Input Gain Matching
Resolution
Programmable Gain
Settling Time for Gain Change
Differential
2
Balanced Differential
(1)
1.5V CMV Recommended
All Inputs
±
3.0
+1.5
V
V
See Typical Performance Curves
10
±
2
14
0
6
pF
%
Bits
dB
Symbol
Periods
%FSR
(2)
Line Input vs Hybrid Input
Four Gains: 0dB, 3.25dB, 6dB, and 9dB
9
Gain + Offset Error
Output Data Coding
Output Data Rate, rxSYNC
(3)
TRANSMIT CHANNEL
Transmit Symbol Rate, f
tx
T1 Transmit –3dB Point
T1 Rate Power Spectral Density
(4)
E1 Transmit –3dB Point
E1 Rate Power Spectral Density
(4)
Transmit Power
(4, 5)
Pulse Output
Common-Mode Voltage, V
CM
Output Resistance
(6)
TRANSCEIVER PERFORMANCE
Uncanceled Echo
(7)
Tested at Each Gain Range
5
Two’s Complement
98
584
kHz
98
584
kHz
kHz
Bellcore TA-NWT-3017 Compliant
196
See Typical Performance Curves
292
See Typical Performance Curves
13
See Typical Performance Curves
AV
DD
/2
1
ETSI RTR/TM-03036 Compliant
kHz
14
dBm
V
DC to 1MHz
rxGAIN = 0dB, Loopback Enabled
rxGAIN = 0dB, Loopback Disabled
rxGAIN = 3.25dB, Loopback Disabled
rxGAIN = 6dB, Loopback Disabled
rxGAIN = 9dB, Loopback Disabled
–67
–67
–69
–71
–73
dB
dB
dB
dB
dB
DIGITAL INTERFACE
(6)
Logic Levels
V
IH
V
IL
V
OH
V
Receive Channel Interface
t
rx1
|I
IH
| < 10
μ
A
|I
IL
| < 10
μ
A
I
OH
= –20
μ
A
I
OL
= 20
μ
A
DV
–1
–0.3
DV
DD
–0.5
DV
+0.3
+0.8
V
V
V
V
+0.4
rxCLK Period
rxCLK Duty Cycle
rxSYNC to rxCLK Setup Time
rxCLK to rxSYNC Hold Time
rxCLK to rxD13 - rxD0 Delay
35
45
10
10
215
55
ns
%
ns
ns
ns
t
rx2
t
rx3
t
50
Transmit Channel Interface
t
tx1
t
tx2
t
tx3
POWER
Analog Power Supply Voltage
Analog Power Supply Voltage
Digital Power Supply Voltage
Digital Power Supply Voltage
Power Dissipation
(4, 5, 8)
Power Dissipation
(4, 5, 8)
PSRR
TEMPERATURE RANGE
Operating
(6)
txCLK Period
txCLK Pulse Width
Basic txDAT Pulse Unit
1.7
50
10.2
μ
s
ns
ns
t
tx1
/96
Specification
Operating Range
Specification
Operating Range
DV
DD
= 3.3V
DV
DD
= 5V
5
V
V
V
V
4.75
5.25
3.3
3.15
5.25
250
300
mW
mW
dB
60
–40
+85
°
C
NOTES: (1) With a balanced differential signal, the positive input is 180
°
out of phase with the negative input, therefore the actual voltage swing about the common
mode voltage on each pin is
±
1.5V to achieve a differential input range of
±
3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the
symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (27dBm output from
txLINE
and txLINE
). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Guaranteed by design and characterization. (7)
Uncanceled Echo is a measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion
of Specifications section of this data sheet for more information. (8) Power dissipation includes only the power dissipated within the component and does not include
power dissipated in the external loads. See the Discussion of Specifications section for more information.
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AFE1105 制造商:BB 制造商全稱:BB 功能描述:HDSL/MDSL ANALOG FRONT END