參數(shù)資料
型號: ADXL210AE
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調(diào)理
英文描述: Low-Cost 10 g Dual-Axis Accelerometer with Duty Cycle
中文描述: SPECIALTY ANALOG CIRCUIT, CQCC8
封裝: CERAMIC, LCC-8
文件頁數(shù): 9/12頁
文件大?。?/td> 169K
代理商: ADXL210AE
REV. 0
ADXL210E
–9–
Setting the Bandwidth Using C
X
and C
Y
The ADXL210E has provisions for bandlimiting the X
FILT
and
Y
FILT
pins. Capacitors must be added at these pins to implement
low-pass filtering for antialiasing and noise reduction. The equa-
tion for the 3 dB bandwidth is:
F
3
dB
=
1
2
π
(32
k
)
×
C
(
x
,
y
)
(
)
or, more simply,
F
3
dB
=
5
μ
F
C
(
X
,
Y
)
The tolerance of the internal resistor (R
FILT
), can vary typically as
much as
±
15% of its nominal value of 32 k
; so the bandwidth
will vary accordingly. A minimum capacitance of 1000 pF for
C
(X, Y)
is required in all cases.
Table I. Filter Capacitor Selection, C
X
and C
Y
Capacitor
Value
0.47
μ
F
0.10
μ
F
0.05
μ
F
0.027
μ
F
0.01
μ
F
0.001
μ
F
Bandwidth
10 Hz
50 Hz
100 Hz
200 Hz
500 Hz
5 kHz
Setting the DCM Period with R
SET
The period of the DCM output is set for both channels by a single
resistor from R
SET
to ground. The equation for the period is:
T
2
=
R
SET
(
)
125
M
A 125 k
resistor will set the duty cycle repetition rate to approxi-
mately 1 kHz, or 1 ms. The device is designed to operate at duty
cycle periods between 0.5 ms and 10 ms.
Table II. Resistor Values to Set T2
T2
R
SET
125 k
250 k
625 k
1.25 M
1 ms
2 ms
5 ms
10 ms
Note that the R
SET
should always be included, even if only an
analog output is desired. Use an R
SET
value between 500 k
and 2 M
when taking the output from X
FILT
or Y
FILT
. The R
SET
resistor should be placed close to the T2 Pin to minimize parasitic
capacitance at this node.
Selecting the Right Accelerometer
For most tilt sensing applications the ADXL202E is the most
appropriate accelerometer. Its higher sensitivity (12.5%/
g)
allows
the user to use a lower speed counter for PWM decoding while
maintaining high resolution. The ADXL210E should be used in
applications where accelerations of greater than
±
2
g
are expected.
DESIGN PROCEDURE FOR THE ADXL210E
The design procedure for using the ADXL210E with a duty cycle
output involves selecting a duty cycle period and a filter capacitor.
A proper design will take into account the application requirements
for bandwidth, signal resolution and acquisition time, as discussed
in the following sections.
Decoupling Capacitor C
DC
A 0.1
μ
F capacitor is recommended from V
DD
to COM for power
supply decoupling.
ST
The ST pin controls the self-test feature. When this pin is set to V
DD
,
an electrostatic force is exerted on the beam of the accelerometer.
The resulting movement of the beam allows the user to test if the
accelerometer is functional. The typical change in output will be 3%
at the duty cycle outputs (corresponding to 800 m
g
). This pin
may be left open circuit or connected to common in normal use.
Duty Cycle Decoding
The ADXL210E
s digital output is a duty cycle modulator.
Acceleration is proportional to the ratio T1/T2. The nominal
output of the ADXL210E is:
0
g
= 50%
Duty Cycle
Scale factor is 4% Duty Cycle Change per
g
These nominal values are affected by the initial tolerance of the
device including zero
g
offset error and sensitivity error.
T2 does not have to be measured for every measurement cycle.
It need only be updated to account for changes due to tempera-
ture (a relatively slow process). Since the T2 time period is shared
by both X and Y channels, it is necessary only to measure it on
one channel of the ADXL210E. Decoding algorithms for various
microcontrollers have been developed. Consult the appropriate
Application Note.
ANALOG
TO
DUTY
CYCLE
(ADC)
C
O
U
N
T
E
R
P
X
OUT
Y
OUT
DEMOD
DEMOD
R
FILT
32k
R
FILT
32k
ADXL210E
R
SET
T2
C
Y
Y
FILT
SELF-TEST
X
FILT
C
X
OSCILLATOR
COM
Y SENSOR
X SENSOR
3V TO 5.25V
V
DD
C
DC
T1
T2
A(
g
) = (T1/T2
0.5)/4%
0
g
= 50% DUTY CYCLE
T2 = R
SET
/125M
Figure 3. Block Diagram
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