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參數(shù)資料
| 型號： | ADV7393 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | 低功耗，芯片尺寸10位標(biāo)清/高清視頻編碼器 |
| 文件頁數(shù)： | 57/96頁 |
| 文件大?。?/td> | 1209K |
| 代理商： | ADV7393 |
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ADV7390/ADV7391/ADV7392/ADV7393
Rev. 0 | Page 57 of 96
0
Figure 76. Input Signal to ED/HD Adaptive Filter
0
Figure 77. Output Signal from ED/HD Adaptive Filter (Mode A)
When changing the adaptive filter mode to Mode B
(Subaddress 0x35, Bit 6), the output shown in Figure 78
can be obtained.
0
Figure 78. Output Signal from ED/HD Adaptive Filter (Mode B)
SD DIGITAL NOISE REDUCTION
Subaddress 0xA3 to Subaddress 0xA5
Digital noise reduction (DNR) is applied to the Y data only.
A filter block selects the high frequency, low amplitude compo-
nents of the incoming signal (DNR input select). The absolute
value of the filter output is compared to a programmable
threshold value (DNR threshold control). There are two DNR
modes available: DNR mode and DNR sharpness mode.
In DNR mode, if the absolute value of the filter output is
smaller than the threshold, it is assumed to be noise. A
programmable amount (coring gain border, coring gain data) of
this noise signal is subtracted from the original signal. In DNR
sharpness mode, if the absolute value of the filter output is less
than the programmed threshold, it is assumed to be noise as
before. However, if the level exceeds the threshold, now being
identified as a valid signal, a fraction of the signal (coring gain
border, coring gain data) is added to the original signal to boost
high frequency components and sharpen the video image.
In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels
× 16 pixels for MPEG1 systems (block size control). DNR can
be applied to the resulting block transition areas known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels
(border area).
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
CORING GAIN DATA
CORING GAIN BORDER
GAIN
DNR CONTROL
FILTER
OUTPUT
> THRESHOLD
INPUT FILTER
BLOCK
FILTER OUTPUT
< THRESHOLD
DNR OUT
+
+
MAIN SIGNAL PATH
ADD SIGNAL
ABOVE
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
DNR
SHARPNESS
MODE
NOISE
SIGNAL PATH
Y DATA
INPUT
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
CORING GAIN DATA
CORING GAIN BORDER
GAIN
DNR CONTROL
FILTER
OUTPUT
< THRESHOLD
INPUT FILTER
BLOCK
FILTER OUTPUT
> THRESHOLD
DNR OUT
MAIN SIGNAL PATH
SUBTRACT
SIGNAL IN
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
DNR MODE
NOISE
SIGNAL PATH
Y DATA
INPUT
–
+
0
Figure 79. SD DNR Block Diagram
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| ADV7393BCPZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADV7393BCPZ | 功能描述:IC DAC VIDEO HDTV 10BIT 40LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7393BCPZ-REEL | 功能描述:IC DAC ENCODER VID HDTV 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7393-DBRDZ | 功能描述:BOARD EVAL FOR ADV7393 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| ADV7393EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7393WBCPZ | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays |
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