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參數(shù)資料
| 型號： | ADV7393 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | 低功耗，芯片尺寸10位標清/高清視頻編碼器 |
| 文件頁數(shù)： | 47/96頁 |
| 文件大小： | 1209K |
| 代理商： | ADV7393 |
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ADV7390/ADV7391/ADV7392/ADV7393
Rev. 0 | Page 47 of 96
LCC1
SFL
P19 TO
P10
VIDEO
DECODER
CLKIN
SFL/MISO
PIXEL PORT
5
RTC
LOW
128
TIME SLOT 01
13
0
14
21
19
F
SC
PLL INCREMENT
2
VALID
SAMPLE
INVALID
SAMPLE
6768
0
RESET BIT
4
RESERVED
ADV739x
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
1
FOR EXAMPLE, VCR OR CABLE.
2
F
SC
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx F
DDS REGISTER IS
F
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS.
3
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
4
RESET ADV739x DDS.
5
REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 “INPUT CONFIGURATION” TABLES FOR PIXEL DATA PIN ASSIGNMENTS.
COMPOSITE
VIDEO
1
H/L TRANSITION
COUNT START
14 BITS
SUBCARRIER
PHASE
SEQUENCE
BIT
3
DAC 1
DAC 2
DAC 3
4 BITS
RESERVED
0
Figure 64. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, that is, in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming VSYNC signal and when the analog output matches
the incoming VSYNC signal.
This control is available in all slave-timing modes except
Slave Mode 0.
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV739x is able to accept input data that contains vertical
blanking interval (VBI) data (such as CGMS, WSS, VITS) in
SD, ED, and HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;
Subaddress 0x83, Bit 4 for SD), VBI data is not present at the
output and the entire VBI is blanked. These control bits are
valid in all master and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be
inserted on Line 13 to Line 42 of each frame, or on Line 6 to
Lind 43 for the ITU-R BT.1358 (625p) standard.
VBI data can be present on Line 10 to Line 20 for NTSC and on
Line 7 to Line 22 for PAL.
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
If CGMS is enabled and VBI is disabled, the CGMS data is
nevertheless available at the output.
SD SUBCARRIER FREQUENCY REGISTERS
Subaddress 0x8C to Subaddress 0x8F
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the following
equation:
32
2
MHz
27
×
=
line
video
one
in
cycles
clock
of
Number
line
video
one
in
periods
subcarrier
of
Number
Register
Frequency
Subcarrier
where the sum is rounded to the nearest integer.
For example, in NTSC mode:
569408543
2
1716
5
227
32
=
×
=
Value
Register
Subcarrier
where:
Subcarrier Register Value
= 569408543d = 0×21F07C1F
SD F
SC
Register 0: 0x1F
SD F
SC
Register 1: 0x7C
SD F
SC
Register 2: 0xF0
SD F
SC
Register 3: 0x21
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