參數(shù)資料
型號(hào)： ADV7330KST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat 11-Bit Triple DAC Video Encoder
中文描述： COLOR SIGNAL ENCODER, PQFP64
封裝： PLASTIC, LEAD FREE, MS-026BCD, LQFP-64
文件頁數(shù)： 48/76頁
文件大?。?/td> 1378K
代理商： ADV7330KST
REV. B
–48–
ADV7330
Block Size Control [Address 64h, Bit 7]
This bit is used to select the size of the data blocks to be processed.
Setting the block size control function to a Logic 1 defines a
16 pixel
×
16 pixel data block and a Logic 0 defines an 8 pixel
×
8 pixel data block, where one pixel refers to two clock cycles at
27 MHz.
DNR Input Select Control [Address 65h, Bit 2–0]
Three bits are assigned to select the filter that is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that will be DNR processed. Figure 42
shows the filter responses selectable with this control.
FILTER C
FILTER B
FILTER A
FILTER D
FREQUENCY (Hz)
00
1
2
3
4
5
6
0.2
0.4
0.6
M
0.8
1.0
Figure 42. DNR Input Select
DNR Mode Control [Address 65h, Bit 4]
This bit controls the DNR mode selected. A Logic 0 selects
DNR mode, a Logic 1 selects DNR sharpness mode.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal will be boosted
(similar to using Extended SSAF filter).
Block Offset Control [Address 65h, Bits 7–4]
Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
SD ACTIVE VIDEO EDGE
[Subaddress 42h, Bit 7]
When the active video edge is enabled, the first three pixels and
the last three pixels of the active video on the luma channel are
scaled in such a way that maximum transitions on these pixels
are not possible. The scaling factors are
×
1/8,
×
1/2, and
×
7/8.
All other active video passes through unprocessed.
SAV/EAV STEP EDGE CONTROL
The ADV7330 has the capability of controlling fast rising and
falling signals at the start and end of active video to minimize
ringing.
An algorithm monitors SAV and EAV and governs when the
edges are too fast. The result will be reduced ringing at the start
and end of active video for fast transitions.
Subaddress 42h, Bit 7 = 1 enables this feature.
100 IRE
0 IRE
100 IRE
12.0 IRE
50 IRE
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
Figure 43. Example for Active Video Edge Functionality
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