參數(shù)資料
型號： ADV7330KST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： Multiformat 11-Bit Triple DAC Video Encoder
中文描述： COLOR SIGNAL ENCODER, PQFP64
封裝： PLASTIC, LEAD FREE, MS-026BCD, LQFP-64
文件頁數(shù)： 42/76頁
文件大小： 1378K
代理商： ADV7330KST
REV. B
–42–
ADV7330
In Case B, the video output signal is reduced. The absolute level
of the sync tip and blanking level both decrease with respect to
the reference video output signal. The overall gain of the signal is
reduced from the reference signal.
The range of this feature is specified for
±
7.5% of the nominal
output from the DACs. For example, if the output current of
the DAC is 4.33 mA, the DAC tune feature can change this
output current from 4.008 mA (–7.5%) to 4.658 mA (+7.5%).
The reset value of the vid_out_ctrl registers is 00h
→
nominal
DAC output current. Table X is an example of how the output
current of the DACs varies for a nominal 4.33 mA output current.
Table X.
DAC
Current
(mA)
Register 0Ah or 0Bh
% Gain
0100 0000 (40h)
0011 1111 (3Fh)
0011 1110 (3Eh)
...
...
0000 0010 (02h)
0000 0001 (01h)
0000 0000 (00h)
4.658
4.653
4.648
...
...
4.43
4.38
4.33
7.5000
7.3820
7.3640
...
...
0.0360
0.0180
0.0000
(I
2
C Reset Value,
Nominal)
1111 1111 (FFh)
1111 1110 (FEh)
...
...
1100 0010 (C2h)
1100 0001 (C1h)
1100 0000 (C0h)
4.25
4.23
...
...
4.018
4.013
4.008
–0.0180
–0.0360
...
...
–7.3640
–7.3820
–7.5000
PROGRAMMABLE DAC GAIN CONTROL
DACs A, B, and C are controlled by Reg 0B. The I
2
C control
registers will adjust the output signal gain up or down from its
absolute level.
CASE B
700mV
300mV
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0Ah, 0Bh
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0Ah, 0Bh
700mV
300mV
Figure 31. Programmable DAC Gain—Positive
and Negative Gain
In Case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the signal
is increased from the reference signal.
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