參數(shù)資料
型號(hào): ADV7324
廠商: Analog Devices, Inc.
英文描述: Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
中文描述: 多格式視頻編碼器216兆赫六噪聲整形的14位DAC
文件頁(yè)數(shù): 74/92頁(yè)
文件大?。?/td> 992K
代理商: ADV7324
ADV7324
APPENDIX 5—SD TIMING MODES
[Subaddress 0x4A]
Rev. 0 | Page 74 of 92
MODE 0 (CCIR-656)—SLAVE OPTION
(TIMING REGISTER 0 TR0 = X X X X X 0 0 0)
The ADV7324 is controlled by the SAV (start active video) and
EAV (end active video) time codes in the pixel data. All timing
information is transmitted using a 4-byte synchronization pattern.
A synchronization pattern is sent immediately before and after
each line during active picture and retrace. If Pin S_VSYNC,
Pin S_HSYNC, and Pin S_BLANK are not used, they should be
tied high during this mode. Blank output is available.
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
YC
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
268 CLOCK
1440 CLOCK
4 CLOCK
4 CLOCK
280 CLOCK
1440 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
0
Figure 108. SD Slave Mode 0
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