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ADV7324
Table 16. Registers 0x44 to 0x49
SR7–
SR0
Register
0x44
Register 3
Rev. 0 | Page 33 of 92
Bit Description
SD VSYNC-3H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
Register Setting
Disabled.
VSYNC= 2.5 lines (PAL),
VSYNC= 3 lines (NTSC).
Genlock disabled.
Subcarrier Reset.
Timing Reset.
RTC enabled.
720 pixels.
710 (NTSC)/702 (PAL).
Chroma enabled.
Chroma disabled.
Enabled.
Disabled.
Disabled.
Enabled.
DAC A = luma, DAC B = chroma.
DAC A = chroma, DAC B = luma.
5.17 μs.
5.31 μs (default).
5.59 μs (must be set for
Macrovision compliance).
Reserved.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
0 must be written to this bit.
0 must be written to this bit.
0 must be written to this bit.
0 must be written to this bit.
Disabled.
Enabled.
8-bit input.
16-bit input.
10-bit input.
20-bit input.
Disabled.
Enabled.
Disabled.
Enabled.
Gamma Curve A.
Gamma Curve B.
Disabled.
11 IRE.
6 IRE.
1.5 IRE.
0 must be written to this bit.
Disabled.
Enabled.
Disabled.
4 clock cycles.
8 clock cycles.
Reserved.
0 must be written to this bit.
0 must be written to this bit.
Reset
Value
0x00
0x45
0x46
SD RTC/TR/SCR
SD Active Video Length
SD Chroma
SD Burst
SD Color Bars
SD DAC Swap
NTSC Color Subcarrier
Adjust (Falling Edge of
HS to Start of Color
Burst)
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
0
1
0
0x00
0x01
SD Mode
Reserved
SD Mode
Register 4
0x47
0x48
0x49
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
0
1
0
0
1
0
1
0x00
0x00
0x00
SD PrPb Scale
SD Y Scale
SD Hue Adjust
SD Brightness
SD Luma SSAF Gain
Reserved
Reserved
Reserved
Reserved
Reserved
SD Double Buffering
SD Input Format
SD Digital Noise
Reduction
SD Gamma Control
SD Gamma Curve
SD Undershoot Limiter
Reserved
SD Black Burst Output on
DAC Luma
SD Chroma Delay
Reserved
Reserved
SD Mode
Register 5
SD Mode
Register 6
SD Mode
Register 7
1
NTSC color bar adjust should be set to 10 b for Macrovision compliance.