參數(shù)資料
型號: ADV7197
廠商: Analog Devices, Inc.
英文描述: Multiformat HDTV Encoder with Three 11-Bit DACs
中文描述: 多格式HDTV編碼器三種11位DAC
文件頁數(shù): 5/20頁
文件大?。?/td> 229K
代理商: ADV7197
REV. 0
–5–
ADV7197
3.3 V TIMING–SPECIFICATIONS
P
arameter
Min
Typ
Max
Unit
Conditions
MPU PORT
1
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
RESET
Low Time
10
0.6
1.3
0.6
0.6
100
400
kHz
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
ns
After This Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
300
300
0.6
100
ANALOG OUTPUTS
2
Analog Output Delay
Analog Output Skew
10
0.5
ns
ns
CLOCK CONTROL AND PIXEL PORT
3
f
CLK
t
CLK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
11
Data Hold Time, t
12
Control Setup Time, t
11
Control Hold Time, t
12
Pipeline Delay
74.25
81
MHz
MHz
ns
ns
ns
ns
ns
ns
Clock Cycles
HDTV Mode
Async Timing Mode
5
5
2.0
4.5
7
4.0
1.5
2.0
16
For 4:4:4 Pixel Input Format
NOTES
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control:
HSYNC
/
SYNC
,
VSYNC
/TSYNC; DV
Specifications subject to change without notice.
(V
AA
= 3.15 V to 3.45 V, V
REF
= 1.235 V, R
SET
= 2470 , R
LOAD
= 300 . All specifications
T
MIN
to T
MAX
[0 C to 70 C] unless otherwise noted.)
CLOCK
PIXEL INPUT
DATA
Y0
Cb0
Y1
Cr0
Y2
Cb1
Cr1
...
...
...
Yxxx
Cbxxx
Yxxx
Crxxx
t
11
t
12
t
9
t
10
t
9
CLOCK HIGH TIME
t
10
CLOCK LOW TIME
t
11
DATA SETUP TIME
t
12
DATA HOLD TIME
Figure 1. 4:2:2 Input Data Format Timing Diagram
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