參數(shù)資料
型號: ADV7197
廠商: Analog Devices, Inc.
英文描述: Multiformat HDTV Encoder with Three 11-Bit DACs
中文描述: 多格式HDTV編碼器三種11位DAC
文件頁數(shù): 17/20頁
文件大小: 229K
代理商: ADV7197
REV. 0
ADV7197
–17–
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.
Optimum performance is achieved by the use of 0.1
μ
F ceramic
capacitors. Each of group of V
AA
or V
DD
pins should be indi-
vidually decoupled to ground. This should be done by placing
the capacitors as close as possible to the device with the capaci-
tor leads as short as possible, thus minimizing lead inductance.
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the ADV7197
should be avoided to minimize noise pickup. Any active pull-up
termination resistors for the digital inputs should be connected
to the digital power plane and not the analog power plane.
Analog Signal Interconnect
The ADV7197 should be located as close as possible to the
output connectors thus minimizing noise pickup and reflections
due to impedance mismatch.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75
. This termi-
nation resistance should be as close as possible to the ADV7197
to minimize reflections.
Any unused inputs should be tied to ground.
300
5k
5k
MPU BUS
4.7k
V
AA
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
ALSB
DV
RESET
CLKIN
R
SET
SDA
SCL
DAC A
V
DD
VSYNC
/TSYNC
ADV7197
UNUSED
INPUTS
SHOULD BE
GROUNDED
DAC B
100
HSYNC
/
SYNC
DAC C
27MHz, 74.25MHz OR
74.1758MHz CLOCK
4.7k
4.7 F
6.3V
300
300
100
2.47k OR 2.82k
10nF
0.1 F
Y OUTPUT
Pr(V) OUTPUT
Pb(U) OUTPUT
V
REF
GND
13, 52
AGND
26, 33
Y0
Y9
Cr0
Cr9
Cb/Cr0
Cb/Cr9
0.1 F
10nF
0.1 F
24, 35
1, 12
V
DD
V
AA
COMP
V
AA
V
AA
V
DD
V
DD
V
DD
Figure 24. Circuit Layout
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