參數(shù)資料
型號(hào)： ADV7195KST
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP52
封裝： PLASTIC, MQFP-52
文件頁(yè)數(shù)： 28/36頁(yè)
文件大?。?/td> 499K
代理商： ADV7195KST
REV. 0
ADV7195
–28–
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4-SR0) = 03H)
Figure 54 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
HDTV Enable (MR30)
When this bit is set to “1,” the ADV7195 reverts to HDTV
mode. When set to “0” the ADV7195 reverts to Progressive
Scan mode (PS mode).
Reserved (MR31–MR32)
A “0” must be written to these bits.
DAC A Control (MR33)
Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
DAC B Control (MR34)
Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.
DAC C Control (MR35)
Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
Reserved (MR36–MR37)
A “0” must be written to these bits.
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
COLOR DELAY
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
MR25 MR24 MR23
Y DELAY
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
MR22 MR21 MR20
MR27
–
MR26
A ZERO MUST
BE WRITTEN
TO THESE BITS
Figure 53. Mode Register 2
MR37
–
MR36
ZERO MUST BE
WRITTEN TO
THESE BITS
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
HDTV ENABLE
MR30
0
1
DISABLE
ENABLE
0
1
POWER-DOWN
NORMAL
MR34
DAC B CONTROL
MR32
–
MR31
ZERO MUST BE
WRITTEN TO
THESE BITS
DAC A CONTROL
MR33
0
1
POWER-DOWN
NORMAL
DAC C CONTROL
MR35
0
1
POWER-DOWN
NORMAL
Figure 54. Mode Register 3
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Figure 53 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
With these bits it is possible to delay the Y signal with respect to
the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 52 demonstrates this facility.
Color Delay (MR23–MR25)
With these bits it is possible to delay the color signals with
respect to the falling edge of the horizontal sync signal by up to
four pixel clock cycles. Figure 52 demonstrates this facility.
Reserved (MR26–MR27)
A “0” must be written to these bits.
Y DELAY
PrPb DELAY
MAX
DELAY
NO DELAY
MAX DELAY
NO DELAY
Y OUTPUT
PrPb OUTPUT
Figure 52. Y and Color Delay
相關(guān)PDF資料
PDF描述
ADV7196 Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
ADV7196A Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
ADV7196AKS Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
ADV7197 Multiformat HDTV Encoder with Three 11-Bit DACs
ADV7197KST Multiformat HDTV Encoder with Three 11-Bit DACs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7195KSZ 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP
ADV7196 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
ADV7196A 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
ADV7196AKS 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision
ADV7197 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat HDTV Encoder with Three 11-Bit DACs
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