參數(shù)資料
型號: ADV7189BBSTZ268H
廠商: Analog Devices, Inc.
英文描述: Multiformat SDTV Video Decoder
中文描述: 標(biāo)清多格式視頻解碼器
文件頁數(shù): 79/104頁
文件大?。?/td> 805K
代理商: ADV7189BBSTZ268H
ADV7189B
Rev. B | Page 79 of 104
Bits
4
Comments
Notes
CAGC[1:0] settings
decide in which
mode CMG[11:0]
operates
Subaddress
0x2D
Register
Chroma
Gain
Control 1
Bit Description
CMG[11:8]. Chroma manual gain
can be used to program a desired
manual chroma gain. Reading back
from this register in AGC mode
gives the current gain.
Reserved
CAGT[1:0]. Chroma automatic gain
timing allows adjustment of the
chroma AGC tracking speed.
7
6
5
3
0
2
1
1
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
Set to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
CMG[11:0] = 750d; gain is
1 in NTSC
CMG[11:0] = 741d; gain is
1 in PAL
LAGC[1:0] settings decide
in which mode LMG[11:0]
operates
Has an effect only if
CAGC[1:0] is set to
auto gain (10)
0x2E
Chroma
Gain
Control 2
lower 8 bits. See CMG[11:8] for
description.
Min value is 0 dec
(G = –60 dB)
Max value is 3750
(Gain = 5)
LMG[11:8]. Luma manual gain can
be used program a desired manual
chroma gain, or to read back the
actual gain value used.
Reserved
LAGT[1:0]. Luma automatic gain
timing allows adjustment of the
luma AGC tracking speed.
x
x
x
x
0
0
1
1
x
0
1
0
1
x
1
x
1
x
x
x
x
x
Set to 1
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
LMG[11:0] = 1234dec; gain
is 1 in NTSC LMG[11:0] =
1266d; gain is 1 in PAL
Only has an effect if
LAGC[1:0] is set to
auto gain (001, 010,
011, or 100)
0x2F
Luma Gain
Control 1
0x30
Luma Gain
Control 2
LMG[7:0]. Luma manual gain can be
used to program a desired manual
chroma gain or read back the
actual used gain value.
Min value
NTSC 1024 (G = 0.85)
PAL (G = 0.81)
Max value
NTSC 2468 (G = 2),
PAL = 2532 (G = 2)
HSE = Hsync end
HSB = Hsync begin
0x31
Reserved
HVSTIM. Selects where within a line
of video the VS signal is asserted.
0
0
1
0
1
0
Set to default
Start of line relative to HSE
Start of line relative to HSB
EAV/SAV codes generated
to suit ADI encoders
Manual VS/Field position
controlled by registers
0x32, 0x33, and 0xE5–
0xEA
Set to default
Set to default
VS goes high in the
middle of the line (even
field)
VS changes state at the
start of the line (even
field)
VS goes high in the
middle of the line (odd
field)
VS changes state at the
start of the line (odd field)
Set to default
VS goes low in the middle
of the line (even field)
VS changes state at the
start of the line (even
field)
VS goes low in the middle
of the line (odd field)
VS changes state at the
start of the line (odd field)
NEWAVMODE. Sets the EAV/SAV
mode.
1
0x32
VS and
FIELD
Control 1
Reserved
Reserved
VSBHE
0
0
0
0
0
0
0
0
0
1
NEWAVMODE bit
must be set high.
1
VSBHO
0
Vsync Field
Control 2
1
Reserved
VSEHE
0
0
0
0
1
0
0
NEWAVMODE bit
must be set high.
1
0x33
Vsync Field
Control 3
VSEHO
0
1
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