參數(shù)資料
型號(hào)： ADV7189BBSTZ268H
廠商： Analog Devices, Inc.
英文描述： Multiformat SDTV Video Decoder
中文描述： 標(biāo)清多格式視頻解碼器
文件頁(yè)數(shù)： 58/104頁(yè)
文件大?。?/td> 805K
代理商： ADV7189BBSTZ268H
ADV7189B
Table 75. PAL Line Enable Bits and
Corresponding Line Numbering
Line Number
(ITU-R BT.470)
12
8
13
9
14
10
15
11
0
12
1
13
2
14
3
15
4
16
5
17
6
18
7
19
8
20
9
21
10
22
11
23
12
321 (8)
13
322 (9)
14
323 (10)
15
324 (11)
0
325 (12)
1
326 (13)
2
327 (14)
3
328 (15)
4
329 (16)
5
330 (17)
6
331 (18)
7
332 (19)
8
333 (20)
9
334 (21)
10
335 (22)
11
336 (23)
IF Compensation Filter
IFFILTSEL[2:0] IF Filter Select Address 0xF8[2:0]
The IFFILTSEL[2:0] register allows the user to compensate for
SAW filter characteristics on a composite input as would be
observed on tuner outputs.
245H
Figure 36 and
246H
Figure 37 show IF
filter compensation for NTSC and PAL.
Rev. B | Page 58 of 104
Line[3:0]
Enable Bit
GDECOL[0]
GDECOL[1]
GDECOL[2]
GDECOL[3]
GDECOL[4]
GDECOL[5]
GDECOL[6]
GDECOL[7]
GDECOL[8]
GDECOL[9]
GDECOL[10]
GDECOL[11]
GDECOL[12]
GDECOL[13]
GDECOL[14]
GDECOL[15]
GDECEL[0]
GDECEL[1]
GDECEL[2]
GDECEL[3]
GDECEL[4]
GDECEL[5]
GDECEL[6]
GDECEL[7]
GDECEL[8]
GDECEL[9]
GDECEL[10]
GDECEL[11]
GDECEL[12]
GDECEL[13]
GDECEL[14]
GDECEL[15]
Comment
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
The options for this feature are as follows:
Bypass Mode (default)
NTSC—consists of three filter characteristics
PAL—consists of three filter characteristics
0
FREQUENCY (MHz)
2.0
4.0
3.5
3.0
2.5
5.0
4.5
–12
–10
–8
–6
–4
–2
0
2
4
6
A
Figure 36. NTSC IF Compensation Filter Responses
0
FREQUENCY (MHz)
3.0
5.0
4.5
4.0
3.5
6.0
5.5
–8
–6
–4
–2
0
2
4
6
A
Figure 37. PAL IF Compensation Filter Responses
See
247H
Table 86 for programming details.
I
P
2
The ADV7189B has a comprehensive interrupt register set. This
map is located in the Register Access. See
248H
Table 85 for details of
the interrupt register map. How to access this map is described
in
249H
Figure 38.
P
C Interrupt System
0
COMMON I
2
C SPACE
ADDRESS 0x00 => 0x3F
ADDRESS 0x0E BIT 6,5 = 00b
ADDRESS 0x0E BIT 6,5 = 01b
I
2
C SPACE
REGISTER ACCESS PAGE 1
ADDRESS 0x40 => 0xFF
NORMAL REGISTER SPACE
I
2
C SPACE
REGISTER ACCESS PAGE 2
ADDRESS 0x40 => 0x4C
INTERRUPT REGISTER SPACE
Figure 38.
Register Access, Page 1 and Page 2
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