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參數(shù)資料
| 型號： | ADV7189 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | 標清多格式視頻解碼器 |
| 文件頁數(shù)： | 42/104頁 |
| 文件大?。?/td> | 890K |
| 代理商： | ADV7189 |
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ADV7189
Table 97. CTA Function
CTA[2:0]
000
001
010
011*
100
101
110
111
*Default value.
SDP SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior
of the HS output pin only:
Rev. A | Page 42 of 104
Description
Not used.
Chroma + 2 chroma pixel (early).
Chroma + 1 chroma pixel (early).
No delay.
Chroma – 1 chroma pixel (late).
Chroma – 2 chroma pixel (late).
Chroma – 3 chroma pixel (late).
Not used.
Beginning of HS signal via HSB[10:0]
End of HS signal via HSE[10:0]
Polarity of HS using PHS
HSB[10:0] HS Begin, Address 0x34, [6:4], Address 0x35, [7:0]
The HS Begin and HS End registers allow the user to freely
position the HS output (pin) within the video line. The values in
HSB[10:0] and HSE[10:0] are measured in pixel units from the
falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal.
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV code FF,00,00,XY (see Figure 20). HSB is set to
00000000010b, which is 2 LLC1 clock cycles from count[0].
Table 98. HSB Function
HSB[10:0]
Description
0x002
The HS pulse starts after the HSB[10:0] pixel after
falling edge of HS.
*Default value.
HSE[10:0] HS End, Address 0x34, [2:0], Address 0x36, [7:0]
The HS Begin and HS End registers allow the user to freely
position the HS output (pin) within the video line. The values in
HSB[10:0] and HSE[10:0] are measured in pixel units from the
falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal.
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV code FF,00,00,XY (see Figure 20). HSE is set to
00000000000b, which is 0 LLC1 clock cycles from count[0].
Table 99. HSE Function
HSE[9:0]
Description
000*
HS pulse ends after HSE[10:0] pixel after falling edge
of HS.
*Default value.
Example
1.
To shift the HS towards active video by 20 LLC1s, add 20
LLC1s to both HSB and HSE. i.e., HSB[10:0] =
[00000010110], HSE[10:0] = [00000010100]
2.
To shift the HS away from active video by 20 LLC1s, add
1696
11
LLC1s to both HSB and HSE (for NTSC).i.e.,
HSB[10:0] = [11000000100], HSE[10:0] = [11000000110]
To move 20 LLC1s away from active video is equal to
subtracting 20 from 1716 and adding the result in binary to
both HSB[10:0] and HSE[10:0].
PHS Polarity HS (SDP), Address 0x37, [7]
The polarity of the HS pin as it comes from the SDP block can
be inverted using the PHS bit.
Table 100. PHS Function
PHS
Description
0*
HS active high.
1
HS active low.
11
1696 is derived from the NTSC total number of pixels = 1716
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7189B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BBSTZ | 功能描述:IC VIDEO DECODER SDTV 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189BBSTZ268H | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BBSTZ268H2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BKST | 制造商:Analog Devices 功能描述: |
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