- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10968 > ADV7181CBSTZ-REEL (Analog Devices Inc)IC VIDEO DECODER SDTV RGB 64LQFP PDF資料下載
參數(shù)資料
| 型號： | ADV7181CBSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER SDTV RGB 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | HDTV |
| 電壓 - 電源，模擬： | 3.15 V ~ 3.45 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADV7181C
Rev. E | Page 11 of 20
Pin No.
Mnemonic
Type1
Description
33, 45
NC
No Connect. These pins are not connected internally.
34
FB
I
Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
35, 36, 46, 47, 48, 49
A
IN1 to AIN6
I
Analog Video Input Channels.
38, 39
CAPY1, CAPY2
I
ADC Capacitor Network. See Figure 9 for a recommended capacitor network
for this pin.
40
AVDD
P
Analog Supply Voltage (3.3 V).
41
REFOUT
O
Internal Voltage Reference Output. See Figure 9 for a recommended capacitor
network for this pin.
42
CML
O
Common-Mode Level Pin (CML) for the Internal ADCs. See Figure 9 for a
recommended capacitor network for this pin.
44
CAPC2
I
ADC Capacitor Network. See Figure 9 for a recommended capacitor network
for this pin.
50
SOG/SOY
I
Sync on Green/Sync on Luma Input. Used in embedded synchronization mode.
51
RESET
I
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms
is required to reset the ADV7181C circuitry.
52
ALSB
I
This pin selects the I2C address for the ADV7181C control and VBI readback
ports. ALSB set to Logic 0 sets the address for a write to Control Port 0x40 and
the readback address for VBI Port 0x21. ALSB set to a Logic 1 sets the address
for a write to Control Port 0x42 and the readback address for VBI Port 0x23.
53
SDATA
I/O
I2C Port Serial Data Input/Output Pin.
54
SCLK
I
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
55
VS_IN
I
VS Input Signal. Used in CP mode for 5-wire timing mode.
56
HS_IN/CS_IN
I
This pin can be configured in CP mode to be either a digital HS input signal or
a digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode.
63
FIELD/DE
O
Field Synchronization Output Signal (All Interlaced Video Modes). This pin
also can be enabled as a data enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
64
VS
O
Vertical Synchronization Output Signal (SDP and CP Modes).
1 G = ground, I = input, O = output, I/O = input/output, and P = power.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC908EY16ACFJER | IC MCU 16K FLASH 8MHZ 32LQFP |
| ADV7181DBCPZ-RL | IC VIDEO DECODER SD/HD 64LFCSP |
| MCF51MM256VLL | IC MCU 32BIT 256K FLASH 100LQFP |
| S9S12XS256J0VAER | MCU 16BIT 256K FLASH 64LQFP |
| VI-B51-IX-B1 | CONVERTER MOD DC/DC 12V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7181CWBSTZ | 制造商:Analog Devices 功能描述:Video Decoder 4ADC 10-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:10-BIT, INTEGRATED, MULTIFORMAT SDTV VIDEO DECODER AND RGB G - Rail/Tube |
| ADV7181CWBSTZ-REEL | 功能描述:Video Decoder IC HDTV 64-LQFP (10x10) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:視頻解碼器 應(yīng)用:HDTV 電壓 - 電源，模擬:3.15 V ~ 3.45 V 電壓 - 電源，數(shù)字:1.65 V ~ 2 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:1,500 |
| ADV7181D | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 10-Channel, Multiformat SDTV/HDTV |
| ADV7181DBCPZ | 制造商:Analog Devices 功能描述:10-BIT, 10 CHANNEL MULTIFORMAT SDTV/HDTV VIDEO DECODER AND R - Trays 制造商:Analog Devices 功能描述:10-BIT SD/HD VIDEO DECODER |
| ADV7181DBCPZ-RL | 功能描述:IC VIDEO DECODER SD/HD 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:* 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。