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參數(shù)資料
| 型號： | ADV7181CBSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER SDTV RGB 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | HDTV |
| 電壓 - 電源，模擬： | 3.15 V ~ 3.45 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
ADV7181C
Data Sheet
Rev. E | Page 10 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
VS
63
FIE
LD
/D
E
62
P
16
61
P
17
60
P
18
59
P
19
58
DV
DD
57
DG
ND
56
HS
_I
N/
CS
_I
N
55
VS_
IN
54
S
CL
K
53
SD
AT
A
52
AL
S
B
51
R
ESET
50
S
OG/S
O
Y
49
A
IN
6
47
AIN4
46
AIN3
45
NC
42
CML
43
AGND
44
CAPC2
48
AIN5
41
REFOUT
40
AVDD
39
CAPY2
37
AGND
36
AIN2
35
AIN1
34
FB
33
NC
38
CAPY1
2
HS/CS
3
DGND
4
DVDDIO
7
P13
6
P14
5
P15
1
INT
8
P12
9
SFL/SYNC_OUT
10
DGND
12
P11
13
P10
14
P9
15
P8
16
P7
11
DVDDIO
17
P6
18
P5
19
P4
20
LLC
21
X
T
AL
1
22
X
T
A
L
23
DV
DD
24
DG
ND
25
P3
26
P2
27
P1
28
P0
29
P
W
RDW
N
30
EL
PF
31
PVD
D
32
AG
ND
PIN 1
ADV7181C
TOP VIEW
(Not to Scale)
07513-
002
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
INT
O
Interrupt. This pin can be active low or active high. When SDP/CP status bits
change, this pin is triggered. The set of events that triggers an interrupt is
under user control.
2
HS/CS
O
HS: Horizontal Synchronization Output Signal (SDP and CP Modes).
CS: Digital Composite Synchronization Signal (CP Mode).
3, 10, 24, 57
DGND
G
Digital Ground.
4, 11
DVDDIO
P
Digital I/O Supply Voltage (3.3 V).
28 to 25, 19 to 12, 8 to 5,
62 to 59
P0 to P19
O
Video Pixel Output Port. Refer to Table 10 for output configuration modes.
9
SFL/SYNC_OUT
O
SFL: Subcarrier Frequency Lock. This pin contains a serial output stream that
can be used to lock the subcarrier frequency when this decoder is connected
to any Analog Devices digital video encoder.
SYNC_OUT: Sliced Synchronization Output Signal Available Only in CP Mode.
20
LLC
O
Line-Locked Output Clock. This pin is for the pixel data (the range is
12.825 MHz to 110 MHz).
21
XTAL1
O
This pin should be connected to the 28.63636 MHz crystal or left as a no connect
if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the
ADV7181C. In crystal mode, the crystal must be a fundamental crystal.
22
XTAL
I
Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,
28.63636 MHz clock oscillator source to clock the ADV7181C.
23, 58
DVDD
P
Digital Core Supply Voltage (1.8 V).
29
PWRDWN
I
A Logic 0 on this pin places the ADV7181C in a power-down mode.
30
ELPF
O
The recommended external loop filter must be connected to this ELPF pin.
31
PVDD
P
PLL Supply Voltage (1.8 V).
32, 37, 43
AGND
G
Analog Ground.
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