參數(shù)資料
型號(hào)： ADV7181BST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat SDTV Video Decoder
中文描述： COLOR SIGNAL DECODER, PQFP64
封裝： LEAD FREE, MS-026BCD, LQFP-64
文件頁數(shù)： 25/96頁
文件大?。?/td> 873K
代理商： ADV7181BST
ADV7181B
The following sections describe the I
2
C signals that can be used
to influence the behavior of the clamping block.
Rev. 0 | Page 25 of 96
Previous revisions of the ADV7181B had controls (FACL/FICL,
fast and fine clamp length) to allow configuration of the length
for which the coarse (fast) and fine current sources are switched
on. These controls were removed on the ADV7181-FT and
replaced by an adaptive scheme.
CCLEN Current Clamp Enable, Address 0x14 [4]
The current clamp enable bit allows the user to switch off the
current sources in the analog front end altogether. This may be
useful if the incoming analog video signal is clamped externally.
When CCLEN is 0, the current sources are switched off.
When CCLEN is 1 (default), the current sources are enabled.
DCT[1:0] Digital Clamp Timing, Address 0x15 [6:5]
The Clamp Timing register determines the time constant of the
digital fine clamp circuitry. It is important to realize that the
digital fine clamp reacts very quickly since it is supposed to
immediately correct any residual dc level error for the active
line. The time constant of the digital fine clamp must be much
quicker than the one from the analog blocks.
By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.
Table 27. DCT Function
DCT[1:0]
Description
00
Slow (TC = 1 sec).
01
Medium (TC = 0.5 sec).
10 (default)
Fast (TC = 0.1 sec).
11
Determined by ADV7181B, depending on the
input video parameters.
DCFE Digital Clamp Freeze Enable, Address 0x15 [4]
This register bit allows the user to freeze the digital clamp loop
at any time. It is intended for users who would like to do their
own clamping. Users should disable the current sources for
analog clamping via the appropriate register bits, wait until the
digital clamp loop settles, and then freeze it via the DCFE bit.
When DCFE to 0 (default), the digital clamp is operational .
When DCFE is 1, the digital clamp loop is frozen.
LUMA FILTER
Data from the digital fine clamp block is processed by three sets
of filters. Note that the data format at this point is CVBS for
CVBS input or luma only for Y/C and YPrPb input formats.
Luma antialias filter (YAA). The ADV7181B receives video
at a rate of 27 MHz. (In the case of 4× oversampled video,
the ADCs sample at 54 MHz, and the first decimation is
performed inside the DPP filters. Therefore, the data rate
into the ADV7181B is always 27 MHz.) The ITU-R BT.601
recommends a sampling frequency of 13.5 MHz. The luma
antialias filter decimates the oversampled video using a
high quality, linear phase, low-pass filter that preserves the
luma signal while at the same time attenuating out-of-band
components. The luma antialias filter (YAA) has a fixed
response.
Luma shaping filters (YSH). The shaping filter block is a
programmable low-pass filter with a wide variety of
responses. It can be used to selectively reduce the luma
video signal bandwidth (needed prior to scaling, for
example). For some video sources that contain high
frequency noise, reducing the bandwidth of the luma signal
improves visual picture quality. A follow-on video
compression stage may work more efficiently if the video is
low-pass filtered.
The ADV7181B has two responses for the shaping filter:
one that is used for good quality CVBS, component, and S-
VHS type sources, and a second for nonstandard CVBS
signals.
The YSH filter responses also include a set of notches for
PAL and NTSC. However, it is recommended to use the
comb filters for YC separation.
Digital resampling filter. This block is used to allow dynamic
resampling of the video signal to alter parameters such as
the time base of a line of video. Fundamentally, the resam-
pler is a set of low-pass filters. The actual response is chosen
by the system with no requirement for user intervention.
Figure 11 through Figure 14 show the overall response of all
filters together. Unless otherwise noted, the filters are set into a
typical wideband mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7181C 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer
ADV7181CBCPZ 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
ADV7181CBCPZ-REEL 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer
ADV7181CBSTZ 功能描述:IC VIDEO DECODER SDTV RGB 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7181CBSTZ-REEL 功能描述:IC VIDEO DECODER SDTV RGB 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
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