參數(shù)資料
型號(hào)： ADV7176KS
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
中文描述： COLOR SIGNAL ENCODER, PQFP44
封裝： PLASTIC, QFP-44
文件頁(yè)數(shù)： 20/36頁(yè)
文件大?。?/td> 447K
代理商： ADV7176KS
ADV7175/ADV7176
REV. A
–20–
HSYNC
to
VSYNC
/FIE LD Delay Control (T R13–T R12)
T hese bits adjust the position of the
HSYNC
output relative to
the FIELD/
VSYNC
output.
HSYNC
to FIE LD Delay Control (T R15–T R14)
When the ADV7175/ADV7176 is in T iming Mode 1, these bits
adjust the position of the
HSYNC
output relative to the FIELD
output rising edge.
VSYNC
Width (T R15–T R14)
When the ADV7175/ADV7176 is in T iming Mode 2, these bits
adjust the
VSYNC
pulse width.
HSYNC
to Pixel Data Adjust (T R17–T R16)
T his enables the
HSYNC
to be adjusted with respect to the
pixel data. T his allows the Cr and Cb components to be
swapped. T his adjustment is available in both master and slave
timing modes.
MODE RE GIST E R 2 MR2 (MR27–MR20)
(Address (SR4-SR0) = 0DH)
Mode Register 2 is an 8-bit wide register.
Figure 38 shows the various operations under the control of
Mode Register 2. T his register can be read from as well written to.
MODE RE GIST E R 2 (MR27–MR20) BIT DE SCRIPT ION
Square Pixel Mode Control (MR20)
T his bit is used to setup square pixel mode. T his is available in
slave mode only. For NT SC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied.
Genlock Control (MR22–MR21)
T hese bits control the genlock feature of the ADV7175/
ADV7176 Setting MR21 to a Logic “1” configures the
SCRESET /RT C pin as an input. Setting MR22 to logic level
“0” configures the SCRESET /RT C pin as a subcarrier reset in-
put. T herefore, the subcarrier will reset to Field 0 following a
low to high transition on the SCRESET /RT C pin. Setting
MR22 to Logic Level “1” configures the SCRESET /RT C pin as
a real time control input.
CLOSE D CAPT IONING E X T E NDE D DAT A RE GIST E RS
1–0 (CE D15–CE D00)
(Address (SR4–SR0) = 09–08H)
T hese 8-bit wide registers are used to set up the closed
captioning extended data bytes. Figure 35 shows how the high
and low bytes are set up in the registers.
BYTE 1
BYTE 0
CED6
CED5
CED3
CED1
CED4
CED2
CED0
CED7
CED14 CED13
CED11
CED9
CED12
CED10
CED8
CED15
Figure 35. Closed Captioning Extended Data Register
CLOSE D CAPT IONING DAT A RE GIST E RS 1–0
(C C D15–C C D00)
(Subaddress (SR4–SR0) = 0B–0AH)
T hese 8-bit wide registers are used to set up the closed
captioning data bytes. Figure 36 shows how the high and low
bytes are set up in the registers.
BYTE 1
BYTE 0
CCD6
CCD5
CCD3
CCD1
CCD4
CCD2
CCD0
CCD7
CCD14 CCD13
CCD11
CCD9
CCD12
CCD10
CCD8
CCD15
Figure 36. Closed Captioning Data Register
T IMING RE GIST E R 1 (T R17–T R10)
(Address (SR4–SR0) = 0CH)
T iming Register 1 is an 8-bit wide register.
Figure 37 shows the various operations under the control of
T iming Register 1. T his register can be read from as well
written to. T his register can be used to adjust the width and
position of the master mode timing signals.
T IMING RE GIST E R 1 (T R17–T R10) BIT DE SCRIPT ION
HSYNC
Width (T R11–T R10)
T hese bits adjust the
HSYNC
pulse width.
TR11
TR10
TR17
TR12
TR13
TR15
TR16
TR14
HSYNC
WIDTH
0
0
1
1
0
1
0
1
1 x T
PCLK
4 x T
PCLK
16 x T
PCLK
128 x T
PCLK
TR11 TR10
Ta
HSYNC
TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
x
x
0
1
T
b
T
b
+ 32μs
TR15 TR14
Tc
HSYNC
TO PIXEL
DATA ADJUSTMENT
TR17 TR16
0
0
1
1
0
1
0
1
0 x T
PCLK
1 x T
PCLK
2 x T
PCLK
3 x T
PCLK
HSYNC
TO
FIELD/
VSYNC
DELAY
TR13 TR12
0
0
1
1
0
1
0
1
1 x T
PCLK
3 x T
PCLK
16 x T
PCLK
64 x T
PCLK
VSYNC
WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 x T
PCLK
4 x T
PCLK
16 x T
PCLK
64 x T
PCLK
LINE 313
LINE 314
LINE 1
Tb
TIMING MODE 1 (MASTER/PAL)
HSYNC
FIELD/
VSYNC
Ta
Tc
Figure 37. Timing Register 1
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