參數(shù)資料
型號(hào): ADV7176KS
廠(chǎng)商: ANALOG DEVICES INC
元件分類(lèi): 顏色信號(hào)轉(zhuǎn)換
英文描述: Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
中文描述: COLOR SIGNAL ENCODER, PQFP44
封裝: PLASTIC, QFP-44
文件頁(yè)數(shù): 12/36頁(yè)
文件大?。?/td> 447K
代理商: ADV7176KS
ADV7175/ADV7176
REV. A
–12–
Mode 1: Master Option.
HSYNC
,
BLANK
,
FIELD
.
(T iming Register 0 T R0 = X X X X X 0 1 1)
In this mode the ADV7175/ADV7176 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when
HSYNC
is low indicates a new frame i.e., vertical retrace. T he
BLANK
signal is optional. When the
BLANK
input is
disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising
clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 17 (NT SC) and Figure 18 (PAL). Figure 19 illus-
trates the
HSYNC
,
BLANK
and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
BLANK
PIXEL
DATA
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
PAL = 132 * CLOCK/2
NTSC = 118 * CLOCK/2
Cb
Y
Cr
Y
Figure 19. Timing Mode 1 Odd/Even Field Transitions
Mode 2: Slave Option.
HSYNC
,
VSYNC
,
BLANK
.
(T iming Register 0 T R0 = X X X X X 1 0 0)
In this mode the ADV7175/ADV7176 accepts horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high indicates the start of an even
field. T he
BLANK
signal is optional. When the
BLANK
input is disabled, the ADV7175/ADV7176 automatically blanks all nor-
mally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NT SC) and Figure 21 (PAL).
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
VSYNC
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
HSYNC
BLANK
VSYNC
Figure 20. Timing Mode 2 (NTSC)
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