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參數(shù)資料
| 型號(hào)： | ADV7127KRUZ140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC VID 140MHZ 3.3/5V 24TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 設(shè)置時(shí)間： | 15ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 240M |
| 產(chǎn)品目錄頁面： | 786 (CN2011-ZH PDF) |
ADV7127
–12–
REV. 0
CIRCUIT DESCRIPTION AND OPERATION
The ADV7127 contains one 10-bit D/A converter, with one
input channel containing a 10-bit register. A reference amplifier
is also integrated on board the part.
Digital Inputs
Ten bits of data (color information) D0–D9 are latched into the
device on the rising edge of each clock cycle. This data is pre-
sented to the 10-bit DAC and is then converted to an analog
output waveform. See Figure 20.
CLOCK
DATA
ANALOG OUTPUTS
, IOUT
DIGITAL INPUTS
D0–D9
IOUT
Figure 20. Video Data Input/Output
All these digital inputs are specified to accept TTL logic levels.
Clock Input
The CLOCK input of the ADV7127 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following equation:
Dot Rate = (Horiz Res)
× (Vert Res) × (Refresh Rate)/
(Retrace Factor)
Horiz Res
= Number of Pixels/Line.
Vert Res
= Number of Lines/Frame.
Refresh Rate
= Horizontal Scan Rate. This is the rate at
which the screen must be refreshed, typically
60 Hz for a noninterlaced system or 30 Hz
for an interlaced system.
Retrace Factor
= Total Blank Time Factor. This takes into
account that the display is blanked for a
certain fraction of the total duration of each
frame (e.g., 0.8).
Therefore, if we have a graphics system with
a 1024
× 1024 resolution, a noninterlaced
60 Hz refresh rate and a retrace factor of 0.8,
then:
Dot Rate
= 1024
× 1024 × 60/0.8
= 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7127
on the rising edge of CLOCK, as previously described in the
Digital Inputs section. It is recommended that the CLOCK
input to the ADV7127 be driven by a TTL buffer (e.g., 74F244).
IOUT
mA
V
17.61
0.66
0
BLACK
LEVEL
WHITE
LEVEL
100 IRE
Figure 21. IOUT Video Output Waveform
Table I. Video Output Truth Table (RSET = 560
,
R
LOAD = 37.5
)
Description
DAC
Data
IOUT
Input
WHITE LEVEL
17.62
0
3FF
VIDEO
Video
17.62 – Video
Data
BLACK LEVEL
0
17.62
000H
Power Management
The
PSAVE input of the ADV7127 puts the part into standby
mode. It is used to reduce power consumption. When
PSAVE
is low, the power may be reduced to approximately 10 mW at
3 V. The ADV7127 in TSSOP package also has a power-down
feature where the entire part, including the voltage reference
circuit, is powered down. In this case, power on the ADV7127
can be reduced to 60
W at 3 V.
Table II. Power Management
Mode
ADV7127 TSSOP
ADV7127 SOIC
Power-Save
10 mW Typically at 3 V 10 mW Typically at 3 V
Power-Down
Power 60
W at 3 V
Not Available
Reference Input
The ADV7127 has an on-board voltage reference. The VREF
pin is normally terminated to VAA through a 0.1
F capacitor.
Alternatively, the part could, if required, be overdriven by an
external 1.23 V reference (AD1580).
A resistance RSET connected between the RSET pin and GND
determines the amplitude of the output video level according to
the following equation:
IOUT (mA) = 7,968
× V
REF(V)/RSET(
)
(1)
Using a variable value of RSET, as shown in Figure 22, allows
for accurate adjustment of the analog output video levels. Use
of a fixed 560
R
SET resistor yields the analog output levels
as quoted in the specification page. These values typically
correspond to the RS-343A video waveform values as shown in
Figure 21.
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